Non-volatile memory with efficient testing during erase

ABSTRACT

When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.

BACKGROUND

The present disclosure relates to non-volatile storage.

Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). One example of non-volatile memory is flash memory (e.g., NAND-type and NOR-type flash memory).

Users of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read that data back. For example, a digital camera may take a photograph and store the photograph in non-volatile memory. Later, a user of the digital camera may view the photograph by having the digital camera read the photograph from the non-volatile memory. Because users often rely on the data they store, it is important to users of non-volatile memory to be able to store data reliably so that the data can be read back successfully.

A defect in a non-volatile memory (e.g., a short or leak between a word line and the channel) can introduce an error into the data being stored. Sometimes a defect appears at the time of manufacturing and sometimes the defect appears during use of the non-volatile memory. To prevent failures of the non-volatile memory when in use due to defects that first present during operation by a user, manufacturers of non-volatile memory include various processes for testing the memory in an effort to detect defects before the non-volatile memory is used to store data. However, users of non-volatile memory want high performance, including fast operational speeds. Therefore, it is desirable for the testing of the memory for defects to use as little time as possible in order to not degrade memory performance.

BRIEF DESCRIPTION OF THE DRAWINGS

Like-numbered elements refer to common components in the different figures.

FIG. 1 is a block diagram depicting one embodiment of a storage system.

FIG. 2A is a block diagram of one embodiment of a memory die.

FIG. 2B is a block diagram of one embodiment of an integrated memory assembly.

FIGS. 2C and 2D depict different embodiments of integrated memory assemblies.

FIG. 3 depicts circuitry used to sense data from non-volatile memory.

FIG. 4 is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure.

FIG. 4A is a block diagram of one embodiment of a memory structure having two planes.

FIG. 4B depicts a top view of a portion of one embodiment of a block of memory cells.

FIG. 4B1 depicts a portion of one embodiment of a block of memory cells.

FIG. 4C depicts a cross sectional view of a portion of one embodiment of a block of memory cells.

FIG. 4D depicts a cross sectional view of a portion of one embodiment of a block of memory cells.

FIG. 4E depicts a cross sectional view of a portion of one embodiment of a block of memory cells.

FIG. 4F is a cross sectional view of one embodiment of a vertical column of memory cells.

FIG. 4G is a schematic of a plurality of NAND strings in multiple sub-blocks of a same block.

FIG. 4H depicts a top view of a portion of one embodiment of a block of memory cells.

FIG. 4I is a schematic of a plurality of NAND strings in multiple sub-blocks of a same block.

FIG. 5A depicts threshold voltage distributions.

FIG. 5B depicts threshold voltage distributions.

FIG. 5C depicts threshold voltage distributions.

FIG. 5D depicts threshold voltage distributions.

FIG. 6 is a flow chart describing one embodiment of a process for programming non-volatile memory.

FIG. 7 depicts the erasing of a NAND string.

FIG. 8 is a signal diagram that depicts the signals applied to a NAND string during erase.

FIG. 9 is a flow chart describing one embodiment of a process for erasing non-volatile memory.

FIG. 10 is a flow chart describing one embodiment of a process for erasing non-volatile memory.

FIG. 11 is a flow chart describing one embodiment of a process for erasing non-volatile memory.

FIGS. 12A and 12B together are a flow chart describing one embodiment of a process for erasing non-volatile memory.

DETAILED DESCRIPTION

To prevent a non-volatile memory from failing during a read operation when the memory is storing and trying to retrieve a user's data, it is proposed to test for defects during the erase process before the data is stored in the memory. Erasing non-volatile memory typically includes applying doses of an erase signal (e.g., erase voltage pulses) and verifying whether the erase was successful (also referred to as erase verify) between the doses of the erase signal.

An erase process is proposed that tests for defects in a manner that reduces the time needed for the tests. When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block of the block, a last even result for the respective NAND string is compared to a last odd result for the respective NAND string. Despite the determination that the first sub-block successfully completed erase verify, it is determined that the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing, without determining that number of NAND strings of the one or more additional sub-blocks that have the last even result different than the last odd result is greater than the limit. The sub-blocks that failed erasing are concluded to be defective (i.e. have a defect) and are retired from further use (e.g., will no longer be used to store host/user data). Because the system does not determine whether number of NAND strings of the one or more additional sub-blocks that have the last even result different than the last odd result is greater than the limit, the time needed to complete the erasing and testing is reduced. In an alternative embodiment, if any sub-blocks of a block are concluded to be defective, then the entire block is retired from further use.

FIG. 1 is a block diagram of one embodiment of a storage system 100 that implements the proposed technology described herein. In one embodiment, storage system 100 is a solid state drive (“SSD”). Storage system 100 can also be a memory card, USB drive or other type of storage system. The proposed technology is not limited to any one type of memory system. Storage system 100 is connected to host 102, which can be a computer, server, electronic device (e.g., smart phone, tablet or other mobile device), appliance, or another apparatus that uses memory and has data processing capabilities. In some embodiments, host 102 is separate from, but connected to, storage system 100. In other embodiments, storage system 100 is embedded within host 102.

The components of storage system 100 depicted in FIG. 1 are electrical circuits. Storage system 100 includes a memory controller 120 connected to non-volatile memory 130 and local high speed volatile memory 140 (e.g., DRAM). Local high speed volatile memory 140 is used by memory controller 120 to perform certain functions. For example, local high speed volatile memory 140 stores logical to physical address translation tables (“L2P tables”).

Memory controller 120 comprises a host interface 152 that is connected to and in communication with host 102. In one embodiment, host interface 152 implements a NVM Express (NVMe) over PCI Express (PCIe). Other interfaces can also be used, such as SCSI, SATA, etc. Host interface 152 is also connected to a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit. NOC's can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communications and brings notable improvements over conventional bus and crossbar interconnections. NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wires and the links of the NOC are shared by many signals. A high level of parallelism is achieved because all links in the NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems keep growing, a NOC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, NOC 154 can be replaced by a bus. Connected to and in communication with NOC 154 is processor 156, ECC engine 158, memory interface 160, and DRAM controller 164. DRAM controller 164 is used to operate and communicate with local high speed volatile memory 140 (e.g., DRAM). In other embodiments, local high speed volatile memory 140 can be SRAM or another type of volatile memory.

ECC engine 158 performs error correction services. For example, ECC engine 158 performs data encoding and decoding, as per the implemented ECC technique. In one embodiment, ECC engine 158 is an electrical circuit programmed by software. For example, ECC engine 158 can be a processor that can be programmed. In other embodiments, ECC engine 158 is a custom and dedicated hardware circuit without any software. In another embodiment, the function of ECC engine 158 is implemented by processor 156.

Processor 156 performs the various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom and dedicated hardware circuit without any software. Processor 156 also implements a translation module, as a software/firmware process or as a dedicated hardware circuit. In many systems, the non-volatile memory is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory die. To implement this system, memory controller 120 (e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies. One example implementation is to maintain tables (i.e. the L2P tables mentioned above) that identify the current translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word “tables” they need not literally be tables. Rather, the logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of a storage system is so large that the local memory 140 cannot hold all of the L2P tables. In such a case, the entire set of L2P tables are stored in a memory die 130 and a subset of the L2P tables are cached (L2P cache) in the local high speed volatile memory 140.

Memory interface 160 communicates with non-volatile memory 130. In one embodiment, memory interface provides a Toggle Mode interface. Other interfaces can also be used. In some example implementations, memory interface 160 (or another portion of controller 120) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory die.

In one embodiment, non-volatile memory 130 comprises one or more memory die. FIG. 2A is a functional block diagram of one embodiment of a memory die 200 that comprises non-volatile memory 130. Each of the one or more memory die of non-volatile memory 130 can be implemented as memory die 200 of FIG. 2A. The components depicted in FIG. 2A are electrical circuits. Memory die 200 includes a memory array 202 that can comprises non-volatile memory cells, as described in more detail below. The array terminal lines of memory array 202 include the various layer(s) of word lines organized as rows, and the various layer(s) of bit lines organized as columns. However, other orientations can also be implemented. Memory die 200 includes row control circuitry 220, whose outputs 208 are connected to respective word lines of the memory array 202. Row control circuitry 220 receives a group of M row address signals and one or more various control signals from System Control Logic circuit 260, and typically may include such circuits as row decoders 222, array terminal drivers 224, and block select circuitry 226 for both reading and writing (programming) operations. Row control circuitry 220 may also include read/write circuitry. Memory die 200 also includes column control circuitry 210 including sense amplifier(s) 230 whose input/outputs 206 are connected to respective bit lines of the memory array 202. Although only single block is shown for array 202, a memory die can include multiple arrays that can be individually accessed. Column control circuitry 210 receives a group of N column address signals and one or more various control signals from System Control Logic 260, and typically may include such circuits as column decoders 212, array terminal receivers or driver circuits 214, block select circuitry 216, as well as read/write circuitry, and I/O multiplexers.

System control logic 260 receives data and commands from memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which comprises one or more electrical circuits) include state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 is programmable by software. In other embodiments, the state machine 262 does not use software and is completely implemented in hardware (e.g., electrical circuits). In another embodiment, the state machine 262 is replaced by a micro-controller or microprocessor, either on or off the memory chip. System control logic 262 can also include a power control module 264 that controls the power and voltages supplied to the rows and columns of the memory structure 202 during memory operations and may include charge pumps and regulator circuit for creating regulating voltages. System control logic 262 includes storage 366 (e.g., RAM, registers, latches, etc.), which may be used to store parameters for operating the memory array 202.

Commands and data are transferred between memory controller 120 and memory die 200 via memory controller interface 268 (also referred to as a “communication interface”). Memory controller interface 268 is an electrical interface for communicating with memory controller 120. Examples of memory controller interface 268 include a Toggle Mode Interface and an Open NAND Flash Interface (ONFI). Other I/O interfaces can also be used.

In some embodiments, all the elements of memory die 200, including the system control logic 260, can be formed as part of a single die. In other embodiments, some or all of the system control logic 260 can be formed on a different die.

In one embodiment, memory structure 202 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping layers.

In another embodiment, memory structure 302 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used.

The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure 202 include ReRAM memories (resistive random access memories), magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure 202 include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.

One example of a ReRAM cross-point memory includes reversible resistance-switching elements arranged in cross-point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.

Another example is magnetoresistive random access memory (MRAM) that stores data by magnetic storage elements. The elements are formed from two ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a particular polarity; the other layer's magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created. MRAM based memory embodiments will be discussed in more detail below.

Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. In other PCM embodiments, the memory cells are programmed by current pulses. Note that the use of “pulse” in this document does not require a square pulse but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or other wave. These memory elements within the individual selectable memory cells, or bits, may include a further series element that is a selector, such as an ovonic threshold switch or metal insulator substrate.

A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, memory construction or material composition, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.

The elements of FIG. 2A can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuitry, which includes all of the other components depicted in FIG. 2A. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of the memory die of storage system 100 that is given over to the memory structure 202; however, this reduces the area of the memory die available for the peripheral circuitry. This can place quite severe restrictions on these elements of the peripheral circuitry. For example, the need to fit sense amplifier circuits within the available area can be a significant restriction on sense amplifier design architectures. With respect to the system control logic 260, reduced availability of area can limit the available functionalities that can be implemented on-chip. Consequently, a basic trade-off in the design of a memory die for the storage system 100 is the amount of area to devote to the memory structure 202 and the amount of area to devote to the peripheral circuitry.

Another area in which the memory structure 202 and the peripheral circuitry are often at odds is in the processing involved in forming these regions, since these regions often involve differing processing technologies and the trade-off in having differing technologies on a single die. For example, when the memory structure 202 is NAND flash, this is an NMOS structure, while the peripheral circuitry is often CMOS based. For example, elements such sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic 260 often employ PMOS devices. Processing operations for manufacturing a CMOS die will differ in many aspects from the processing operations optimized for an NMOS flash NAND memory or other memory cell technologies.

To improve upon these limitations, embodiments described below can separate the elements of FIG. 2A onto separately formed dies that are then bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die) and some or all of the peripheral circuitry elements, including one or more control circuits, can be formed on a separate die (referred to as the control die). For example, a memory die can be formed of just the memory elements, such as the array of memory cells of flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory type. Some or all of the peripheral circuitry, even including elements such as decoders and sense amplifiers, can then be moved on to a separate control die. This allows each of the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS based memory array structure, without worrying about the CMOS elements that have now been moved onto a control die that can be optimized for CMOS processing. This allows more space for the peripheral elements, which can now incorporate additional capabilities that could not be readily incorporated were they restricted to the margins of the same die holding the memory cell array. The two die can then be bonded together in a bonded multi-die memory circuit, with the array on the one die connected to the periphery elements on the other die. Although the following will focus on a bonded memory circuit of one memory die and one control die, other embodiments can use more die, such as two memory die and one control die, for example.

FIG. 2B shows an alternative arrangement to that of FIG. 2A which may be implemented using wafer-to-wafer bonding to provide a bonded die pair. FIG. 2B depicts a functional block diagram of one embodiment of an integrated memory assembly 207. One or more integrated memory assemblies 207 may be used to implement the non-volatile memory 130 of storage system 100. The integrated memory assembly 207 includes two types of semiconductor die (or more succinctly, “die”). Memory die 201 includes memory structure 202. Memory structure 202 includes non-volatile memory cells. Control die 211 includes control circuitry 260, 210, and 220 (as described above). In some embodiments, control die 211 is configured to connect to the memory structure 202 in the memory die 201. In some embodiments, the memory die 201 and the control die 211 are bonded together.

FIG. 2B shows an example of the peripheral circuitry, including control circuits, formed in a peripheral circuit or control die 211 coupled to memory structure 202 formed in memory die 201. Common components are labelled similarly to FIG. 2A. System control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of the column control circuitry 210 and all or a portion of the row control circuitry 220 are located on the memory die 201. In some embodiments, some of the circuitry in the system control logic 260 is located on the on the memory die 201.

System control logic 260, row control circuitry 220, and column control circuitry 210 may be formed by a common process (e.g., CMOS process), so that adding elements and functionalities, such as ECC, more typically found on a memory controller 120 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 120 may also be used to fabricate system control logic 260, row control circuitry 220, and column control circuitry 210). Thus, while moving such circuits from a die such as memory 2 die 201 may reduce the number of steps needed to fabricate such a die, adding such circuits to a die such as control die 211 may not require many additional process steps. The control die 211 could also be referred to as a CMOS die, due to the use of CMOS technology to implement some or all of control circuitry 260, 210, 220.

FIG. 2B shows column control circuitry 210 including sense amplifier(s) 230 on the control die 211 coupled to memory structure 202 on the memory die 201 through electrical paths 206. For example, electrical paths 206 may provide electrical connection between column decoder 212, driver circuitry 214, and block select 216 and bit lines of memory structure 202. Electrical paths may extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of the memory die 201, which are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical paths 206, including a pair of bond pads, which connects to column control circuitry 210. Similarly, row control circuitry 220, including row decoder 222, array drivers 224, and block select 226 are coupled to memory structure 202 through electrical paths 208. Each of electrical path 208 may correspond to a word line, dummy word line, or select gate line. Additional electrical paths may also be provided between control die 211 and memory die 201.

For purposes of this document, the phrases “a control circuit” or “one or more control circuits” can include any one of or any combination of memory controller 120, state machine 262, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, a microcontroller, a microprocessor, and/or other similar functioned circuits. The control circuit can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, FGA, ASIC, integrated circuit, or other type of circuit.

In some embodiments, there is more than one control die 211 and more than one memory die 201 in an integrated memory assembly 207. In some embodiments, the integrated memory assembly 207 includes a stack of multiple control die 211 and multiple memory die 201. FIG. 2C depicts a side view of an embodiment of an integrated memory assembly 207 stacked on a substrate 271 (e.g., a stack comprising control dies 211 and memory dies 201). The integrated memory assembly 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control die 211.

Each control die 211 is affixed (e.g., bonded) to at least one of the memory dies 201. Some of the bond pads 282/284 are depicted. There may be many more bond pads. A space between two dies 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. This solid layer 280 protects the electrical connections between the dies 201, 211, and further secures the dies together. Various materials may be used as solid layer 280, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA.

The integrated memory assembly 207 may for example be stacked with a stepped offset, leaving the bond pads at each level uncovered and accessible from above. Wire bonds 270 connected to the bond pads connect the control die 211 to the substrate 271. A number of such wire bonds may be formed across the width of each control die 211 (i.e., into the page of FIG. 2C).

A memory die through silicon via (TSV) 276 may be used to route signals through a memory die 201. A control die through silicon via (TSV) 278 may be used to route signals through a control die 211. The TSVs 276, 278 may be formed before, during or after formation of the integrated circuits in the semiconductor dies 201, 211. The TSVs may be formed by etching holes through the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.

Solder balls 272 may optionally be affixed to contact pads 274 on a lower surface of substrate 271. The solder balls 272 may be used to couple the integrated memory assembly 207 electrically and mechanically to a host device such as a printed circuit board. Solder balls 272 may be omitted where the integrated memory assembly 207 is to be used as an LGA package. The solder balls 272 may form a part of the interface between integrated memory assembly 207 and memory controller 120.

FIG. 2D depicts a side view of another embodiment of an integrated memory assembly 207 stacked on a substrate 271. The integrated memory assembly 206 of FIG. 2D has three control die 211 and three memory die 201. In some embodiments, there are many more than three memory dies 201 and many more than three control dies 211. In this example, each control die 211 is bonded to at least one memory die 201. Optionally, a control die 211 may be bonded to two or more memory die 201.

Some of the bond pads 282, 284 are depicted. There may be many more bond pads. A space between two dies 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. In contrast to the example in FIG. 2C, the integrated memory assembly 207 in FIG. 2D does not have a stepped offset. A memory die through silicon via (TSV) 276 may be used to route signals through a memory die 201. A control die through silicon via (TSV) 278 may be used to route signals through a control die 211.

Solder balls 272 may optionally be affixed to contact pads 274 on a lower surface of substrate 271. The solder balls 272 may be used to couple the integrated memory assembly 207 electrically and mechanically to a host device such as a printed circuit board. Solder balls 272 may be omitted where the integrated memory assembly 207 is to be used as an LGA package.

As has been briefly discussed above, the control die 211 and the memory die 201 may be bonded together. Bond pads on each die 201, 211 may be used to bond the two dies together. In some embodiments, the bond pads are bonded directly to each other, without solder or other added material, in a so-called Cu-to-Cu bonding process. In a Cu-to-Cu bonding process, the bond pads are controlled to be highly planar and formed in a highly controlled environment largely devoid of ambient particulates that might otherwise settle on a bond pad and prevent a close bond. Under such properly controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension. Such bonds may be formed at room temperature, though heat may also be applied. In embodiments using Cu-to-Cu bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 5 μm to 5 μm. While this process is referred to herein as Cu-to-Cu bonding, this term may also apply even where the bond pads are formed of materials other than Cu.

When the area of bond pads is small, it may be difficult to bond the semiconductor dies together. The size of, and pitch between, bond pads may be further reduced by providing a film layer on the surfaces of the semiconductor dies including the bond pads. The film layer is provided around the bond pads. When the dies are brought together, the bond pads may bond to each other, and the film layers on the respective dies may bond to each other. Such a bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 1 μm to 5 μm. Bonding techniques may be used providing bond pads with even smaller (or greater) sizes and pitches.

Some embodiments may include a film on surface of the dies 201, 211. Where no such film is initially provided, a space between the dies may be under filled with an epoxy or other resin or polymer. The under-fill material may be applied as a liquid which then hardens into a solid layer. This under-fill step protects the electrical connections between the dies 201, 211, and further secures the dies together. Various materials may be used as under-fill material, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA.

FIG. 3 is a block diagram depicting one embodiment of a portion of column control circuitry 210 that is partitioned into a plurality of sense amplifiers 230, and a common portion, referred to as a managing circuit 302. In one embodiment, each sense amplifier 230 is connected to a respective bit line which in turn is connected to one or more NAND strings. In one example implementation, each bit line is connected to six NAND strings, with one NAND string per sub-block. Managing circuit 302 is connected to a set of multiple (e.g., four, eight, etc.) sense amplifiers 230. Each of the sense amplifiers 230 in a group communicates with the associated managing circuit via data bus 304.

Each sense amplifier 230 operates to provide voltages to bit lines (see BL0, BL1. BL2. BL3) during program, verify, erase and read operations. Sense amplifiers are also used to sense the condition (e.g., data state) to a memory cells in a NAND string connected to the bit line that connects to the respective sense amplifier.

Each sense amplifier 230 includes a selector 306 or switch connected to a transistor 308 (e.g., an nMOS). Based on voltages at the control gate 310 and drain 312 of the transistor 308, the transistor can operate as a pass gate or as a bit line clamp. When the voltage at the control gate is sufficiently higher than the voltage on the drain, the transistor operates as a pass gate to pass the voltage at the drain to the bit line (BL) at the source 314 of the transistor. For example, a program-inhibit voltage such as 1-2 V may be passed when pre-charging and inhibiting an unselected NAND string. Or, a program-enable voltage such as 0 V may be passed to allow programming in a selected NAND string. The selector 306 may pass a power supply voltage Vdd, (e.g., 3-4 V) to the control gate of the transistor 308 to cause it to operate as a pass gate.

When the voltage at the control gate is lower than the voltage on the drain, the transistor 308 operates as a source-follower to set or clamp the bit line voltage at Vcg−Vth, where Vcg is the voltage on the control gate 310 and Vth, e.g., 0.7 V, is the threshold voltage of the transistor 308. This assumes the source line is at 0 V. If Vcelsrc is non-zero, the bit line voltage is clamped at Vcg-Vcelsrc-Vth. The transistor is therefore sometimes referred to as a bit line clamp (BLC) transistor, and the voltage Vcg on the control gate 310 is referred to as a bit line clamp voltage, Vblc. This mode can be used during sensing operations such as read and verify operations. The bit line voltage is thus set by the transistor 308 based on the voltage output by the selector 306. For example, the selector 306 may pass Vsense+Vth, e.g., 1.5 V, to the control gate of the transistor 308 to provide Vsense, e.g., 0.8 V, on the bit line. A Vbl selector 316 may pass a relatively high voltage such as Vdd to the drain 312, which is higher than the control gate voltage on the transistor 308, to provide the source-follower mode during sensing operations. Vbl refers to the bit line voltage.

The Vbl selector 316 can pass one of a number of voltage signals. For example, the Vbl selector can pass a program-inhibit voltage signal which increases from an initial voltage, e.g., 0 V, to a program inhibit voltage, e.g., Vbl_inh for respective bit lines of unselected NAND string during a program loop. The Vbl selector 316 can pass a program-enable voltage signal such as 0 V for respective bit lines of selected NAND strings during a program loop.

In one approach, the selector 306 of each sense circuit can be controlled separately from the selectors of other sense circuits. The Vbl selector 316 of each sense circuit can also be controlled separately from the Vbl selectors of other sense circuits.

During sensing, a sense node 318 is charged up to an initial voltage, Vsense_init, such as 3 volts. The sense node is then passed to the bit line via the transistor 308, and an amount of decay of the sense node is used to determine whether a memory cell is in a conductive or non-conductive state. The amount of decay of the sense node also indicates whether a current Icell in the memory cell exceeds a reference current, Iref. A larger decay corresponds to a larger current. If Icell<=Iref, the memory cell is in a non-conductive state and if Icell>Iref, the memory cell is in a conductive state.

In particular, the comparison circuit 320 determines the amount of decay by comparing the sense node voltage to a trip voltage at a sense time. If the sense node voltage decays below the trip voltage, Vtrip, the memory cell is in a conductive state and its Vth is at or below the verify voltage. If the sense node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vth is above the verify voltage. A sense node latch 322 is set to 0 or 1, for example, by the comparison circuit 320 based on whether the memory cell is in a conductive or non-conductive state, respectively. For example, in a program-verify test, a 0 can denote fail and a 1 can denote pass. The bit in the sense node latch can be read out in a state bit scan operation of a scan operation or flipped from 0 to 1 in a fill operation. The bit in the sense node latch 322 can also be used in a lockout scan to decide whether to set a bit line voltage to an inhibit or program level in a next program loop.

Managing circuit 302 comprises a processor 330, four example sets of data latches 340, 342, 344 and 346, and an I/O interface 332 coupled between the sets of data latches and the data bus 334. FIG. 3 shows four example sets of data latches 340, 342, 344 and 346; however, in other embodiments more or less than four can be implemented. In one embodiment, there is one set of latches for each sense amplifier 230. One set of five data latches, e.g., comprising individual latches ADL, BDL, CDL, TDL and XDL, can be provided for each sense circuit. In some cases, a different number of data latches may be used. In a three bit per memory cell embodiment, ADL stores a bit for a lower page of data, BDL stores a bit for a middle page of data, CDL stores a bit for an upper page of data and XDL serves as an interface latch for storing/latching data from the memory controller. TDL can be used to store a last comparison of an even result to an odd result, as described below.

Processor 330 performs computations, such as to determine the data stored in the sensed memory cell and store the determined data in the set of data latches. Each set of data latches 340-346 is used to store data bits determined by processor 330 during a read operation, and to store data bits imported from the data bus 334 during a program operation which represent write data meant to be programmed into the memory. I/O interface 332 provides an interface between data latches 340-346 and the data bus 334.

During reading, the operation of the system is under the control of state machine 262 that controls the supply of different control gate voltages to the addressed memory cell. As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuit may trip at one of these voltages and a corresponding output will be provided from the sense amplifier to processor 330 via the data bus 304. At that point, processor 330 determines the resultant memory state by consideration of the tripping event(s) of the sense circuit and the information about the applied control gate voltage from the state machine via input lines 348. It then computes a binary encoding for the memory state and stores the resultant data bits into data latches 340-346.

Some implementations can include multiple processors 330. In one embodiment, each processor 330 will include an output line (not depicted) such that each of the output lines is connected in a wired-OR connection. A wired OR connection or line can be provided by connecting multiple wires together at a node, where each wire carries a high or low input signal from a respective processor, and an output of the node is high if any of the input signals is high. In some embodiments, the output lines are inverted prior to being connected to the wired-OR line. This configuration enables a quick determination during a program verify test of when the programming process has completed because the state machine receiving the wired-OR can determine when all bits being programmed have reached the desired level. For example, when each bit has reached its desired level, a logic zero for that bit will be sent to the wired-OR line (or a data one is inverted). When all bits output a data 0 (or a data one inverted), then the state machine knows to terminate the programming process. Because each processor communicates with eight sense circuits, the state machine needs to read the wired-OR line eight times, or logic is added to processor 330 to accumulate the results of the associated bit lines such that the state machine need only read the wired-OR line one time. Similarly, by choosing the logic levels correctly, the global state machine can detect when the first bit changes its state and change the algorithms accordingly.

During program or verify operations for memory cells, the data to be programmed (write data) is stored in the set of data latches 340-346 from the data bus 334. During reprogramming, a respective set of data latches of a memory cell can store data indicating when to enable the memory cell for reprogramming based on the program pulse magnitude.

The program operation, under the control of the state machine 262, applies a series of programming voltage pulses to the control gates of the addressed memory cells. Each voltage pulse may be stepped up in magnitude from a previous program pulse by a step size in a processed referred to as incremental step pulse programming. Each program voltage is followed by a verify operation to determine if the memory cells has been programmed to the desired memory state. In some cases, processor 330 monitors the read back memory state relative to the desired memory state. When the two are in agreement, processor 330 sets the bit line in a program inhibit mode such as by updating its latches. This inhibits the memory cell coupled to the bit line from further programming even if additional program pulses are applied to its control gate.

FIG. 4 is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array/structure that can comprise memory structure 202, which includes a plurality non-volatile memory cells arranged as vertical NAND strings. For example, FIG. 4 shows a portion 400 of one block of memory. The structure depicted includes a set of bit lines BL positioned above a stack 401 of alternating dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. As will be explained below, in one embodiment the alternating dielectric layers and conductive layers are divided into four or five (or a different number of) regions (also referred to as sub-blocks) by isolation regions IR. FIG. 4 shows one isolation region IR separating two sub-blocks. Below the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that in FIG. 4 , the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. More details of the three dimensional monolithic memory array that comprises memory structure 202 is provided below.

FIG. 4A is a block diagram explaining one example organization of memory structure 202, which is divided into two planes 402 and 404. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a block of memory cells is a unit of erase. That is, all memory cells of a block are erased together. In other embodiments, blocks can be divided into sub-blocks and the sub-blocks can be the unit of erase. Memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable the signaling and selection circuits. In some embodiments, a block represents a groups of connected memory cells as the memory cells of a block share a common set of word lines. For example, the word lines for a block are all connected to all of the vertical NAND strings for that block. Although FIG. 4A shows two planes 402/404, more or less than two planes can be implemented. In some embodiments, memory structure 202 includes eight planes.

FIGS. 4B-4G depict an example three dimensional (“3D”) NAND structure that corresponds to the structure of FIG. 4 and can be used to implement memory structure 202 of FIGS. 2A and 2B. FIG. 4B is a block diagram depicting a top view of a portion 406 of Block 2 of plane 402. As can be seen from FIG. 4B, the block depicted in FIG. 4B extends in the direction of 432. In one embodiment, the memory array has many layers; however, FIG. 4B only shows the top layer.

FIG. 4B depicts a plurality of circles that represent the vertical columns, which correspond to the memory holes. Each of the vertical columns include multiple select transistors (also referred to as a select gate or selection gate) and multiple memory cells. In one embodiment, each vertical column implements a NAND string. For example, FIG. 4B labels a subset of the vertical columns/NAND strings 432, 436, 446. 456, 462, 466, 472, 474 and 476.

FIG. 4B also depicts a set of bit lines 415, including bit lines 411, 412, 413, 414, . . . 419. FIG. 4B shows twenty four bit lines because only a portion of the block is depicted. It is contemplated that more than twenty four bit lines connected to vertical columns of the block. Each of the circles representing vertical columns has an “x” to indicate its connection to one bit line. For example, bit line 411 is connected to vertical columns 436, 446, 456, 466 and 476.

The block depicted in FIG. 4B includes a set of isolation regions 482, 484, 486 and 488, which are formed of SiO₂; however, other dielectric materials can also be used. Isolation regions 482, 484, 486 and 488 serve to divide the top layers of the block into five regions; for example, the top layer depicted in FIG. 4B is divided into regions 430, 440, 450, 460 and 470 all of which are referred to as sub-blocks. In one embodiment, the isolation regions only divide the layers used to implement select gates so that NAND strings in different sub-blocks can be independently selected. In one example implementation, a bit line connects to one vertical column/NAND string in each of regions (sub-blocks) 430, 440, 450, 460 and 470. In that implementation, each block has twenty four rows of active columns and each bit line connects to five rows in each block. In one embodiment, all of the five vertical columns/NAND strings connected to a common bit line are connected to the same set of word lines; therefore, the system uses the drain side selection lines to choose one (or another subset) of the five to be subjected to a memory operation (program, verify, read, and/or erase).

FIG. 4B also shows Line Interconnects LI, which are metal connections to the source line SL from above the memory array. Line Interconnects LI are positioned adjacent regions 430 and 470.

Although FIG. 4B shows each region 430, 440, 450, 460 and 470 having four rows of vertical columns, five regions and twenty four rows of vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of vertical columns per region and more or less rows of vertical columns per block. FIG. 4B also shows the vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the vertical columns are not staggered.

FIG. 4B1 depicts a portion of one embodiment of a block of memory cells. Each of the circles represents a memory hole. In some embodiments, isolation regions are formed on dummy memory holes (DMH), as shown in the embodiment of FIG. 4B1. Bit lines are not connected to dummy memory holes and hence, data is not stored in dummy memory holes. The isolation regions (IR0, IR1, IR2, IR3) are filled with SiO₂ or other non-conducting dielectric materials. The isolation regions (IR0, IR1, IR2, IR3) serve to divide the top layers of the block into five regions referred to herein as sub-blocks (sub0, sub1, sub2, sub3, sub4). In some embodiments, the isolation regions (IR0, IR1, IR2, IR3) only divide the layers used to implement select gates (e.g., SGD) so that NAND strings in different sub-blocks can be independently selected.

FIG. 4C depicts a portion of one embodiment of a three dimensional memory structure 202 showing a cross-sectional view along line AA of FIG. 4B. This cross sectional view cuts through vertical columns (NAND strings) 472 and 474 of region 470 (see FIG. 4B). The structure of FIG. 4C includes three drain side select layers SGD0, SGD1 and SGD2; three source side select layers SGS0, SGS1, and SGS2; three dummy word line layers DD0, DD1, and DDS; two hundred and forty word line layers WL0-WL239 for connecting to data memory cells, and two hundred and fifty dielectric layers DL0-DL249. Other embodiments can implement more or less than the numbers described above for FIG. 4C. In one embodiment, SGD0, SGD1 and SGD2 are connected together; and SGS0, SGS1 and SGS2 are connected together. In other embodiments, more or less number of SGDs (greater or lesser than three) are connected together, and more or less number of SGSs (greater or lesser than three) connected together.

Vertical columns 472 and 474 are depicted protruding through the drain side select layers, source side select layers, dummy word line layers and word line layers. In one embodiment, each vertical column comprises a vertical NAND string. Below the vertical columns and the layers listed below is substrate 453, an insulating film 454 on the substrate, and source line SL. The NAND string of vertical column 442 has a source end at a bottom of the stack and a drain end at a top of the stack. As in agreement with FIG. 4B, FIG. 4C show vertical column 472 connected to bit line 414 via connector 417.

For ease of reference, drain side select layers; source side select layers, dummy word line layers and data word line layers collectively are referred to as the conductive layers. In one embodiment, the conductive layers are made from a combination of TiN and Tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as Tungsten, metal silicide, such as nickel silicide, tungsten silicide, aluminum silicide or the combination thereof. In some embodiments, different conductive layers can be formed from different materials. Between conductive layers are dielectric layers DL0-DL249. For example, dielectric layers DL240 is above word line layer WL235 and below word line layer WL236. In one embodiment, the dielectric layers are made from SiO₂. In other embodiments, other dielectric materials can be used to form the dielectric layers.

The non-volatile memory cells are formed along vertical columns which extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. The word line layers WL0-W239 connect to memory cells (also called data memory cells). Dummy word line layers DD0, DD1 and DS connect to dummy memory cells. A dummy memory cell does not store and is not eligible to store host data (data provided from the host, such as data from a user of the host), while a data memory cell is eligible to store host data. In some embodiments, data memory cells and dummy memory cells may have a same structure. Drain side select layers SGD0, SGD1, and SGD2 are used to electrically connect and disconnect NAND strings from bit lines. Source side select layers SGS0, SGS1, and SGS2 are used to electrically connect and disconnect NAND strings from the source line SL.

FIG. 4D depicts a portion of one embodiment of a three dimensional memory structure 202 showing a cross-sectional view along line BB of FIG. 4B. This cross sectional view cuts through vertical columns (NAND strings) 432 and 434 of region 430 (see FIG. 4B). FIG. 4D shows the same alternating conductive and dielectric layers as FIG. 4C. FIG. 4D also shows isolation region 482. Isolation regions 482, 484, 486 and 488) occupy space that would have been used for a portion of the memory holes/vertical columns/NAND stings. For example, isolation region 482 occupies space that would have been used for a portion of vertical column 434. More specifically, a portion (e.g., half the diameter) of vertical column 434 has been removed in layers SDG0, SGD1, SGD2, and DD0 to accommodate isolation region 482. Thus, while most of the vertical column 434 is cylindrical (with a circular cross section), the portion of vertical column 434 in layers SDG0, SGD1, SGD2, and DD0 has a semi-circular cross section. In one embodiment, after the stack of alternating conductive and dielectric layers is formed, the stack is etched to create space for the isolation region and that space is then filled in with SiO₂.

FIG. 4E depicts a portion of one embodiment of a three dimensional memory structure 202 showing a cross-sectional view along line CC of FIG. 4B. This cross sectional view cuts through vertical columns (NAND strings) 452 and 4624 (see FIG. 4B). FIG. 4E shows the same alternating conductive and dielectric layers as FIG. 4C. FIG. 4E also shows isolation region 486 cutting into vertical columns (NAND string) 452.

FIG. 4F depicts a cross sectional view of region 429 of FIG. 4C that includes a portion of vertical column 472. In one embodiment, the vertical columns are round; however, in other embodiments other shapes can be used. In one embodiment, vertical column 472 includes an inner core layer 490 that is made of a dielectric, such as SiO₂. Other materials can also be used. Surrounding inner core 490 is polysilicon channel 491. Materials other than polysilicon can also be used. Note that it is the channel 491 that connects to the bit line and the source line. Surrounding channel 491 is a tunneling dielectric 492. In one embodiment, tunneling dielectric 492 has an ONO structure. Surrounding tunneling dielectric 492 is charge trapping layer 493, such as (for example) Silicon Nitride. Other memory materials and structures can also be used. The technology described herein is not limited to any particular material or structure.

FIG. 4F depicts dielectric layers DL239, DL240, DL241, DL242 and DL243, as well as word line layers WL234, WL235, WL236, WL237, and WL238. Each of the word line layers includes a word line region 496 surrounded by an aluminum oxide layer 497, which is surrounded by a blocking oxide layer 498. In other embodiments, the blocking oxide layer can be a vertical layer parallel and adjacent to charge trapping layer 493. The physical interaction of the word line layers with the vertical column forms the memory cells. Thus, a memory cell, in one embodiment, comprises channel 491, tunneling dielectric 492, charge trapping layer 493, blocking oxide layer 498, aluminum oxide layer 497 and word line region 496. For example, word line layer WL238 and a portion of vertical column 472 comprise a memory cell MC1. Word line layer WL237 and a portion of vertical column 472 comprise a memory cell MC2. Word line layer WL236 and a portion of vertical column 472 comprise a memory cell MC3. Word line layer WL235 and a portion of vertical column 472 comprise a memory cell MC4. Word line layer WL234 and a portion of vertical column 472 comprise a memory cell MC5. In other architectures, a memory cell may have a different structure; however, the memory cell would still be the storage unit.

When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 493 which is associated with (e.g. in) the memory cell. These electrons are drawn into the charge trapping layer 493 from the channel 491, through the tunneling dielectric 492, in response to an appropriate voltage on word line region 496. The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge. In one embodiment, the programming is achieved through Fowler-Nordheim tunneling of the electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasing is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL.

FIG. 4G is a schematic diagram of a portion of the memory array 202 depicted in in FIGS. 4-4F. FIG. 4G shows physical data word lines WL0-WL239 running across the entire block. The structure of FIG. 4G corresponds to a portion 406 in Block 2 of FIG. 4A, including bit line 411. Within the block, in one embodiment, each bit line is connected to five NAND strings. Thus, FIG. 4G shows bit line connected to NAND string NS0 (which corresponds to vertical column 436), NAND string NS1 (which corresponds to vertical column 446), NAND string NS2 (which corresponds to vertical column 456), NAND string NS3 (which corresponds to vertical column 466), and NAND string NS4 (which corresponds to vertical column 476). As mentioned above, in one embodiment, SGD0, SGD1 and SGD2 are connected together to operate as a single logical select gate for each sub-block separated by isolation regions (482, 484, 486 and 486) to form SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4. SGS0, SG1 and SGS2 are also connected together to operate as a single logical select gate that is represented in FIG. 4G as SGS. Although the select gates SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4 are isolated from each other due to the isolation regions, the data word lines WL0-WL239 of each sub-block are connected together.

The isolation regions (482, 484, 486 and 486) are used to allow for separate control of sub-blocks. A first sub-block corresponds to those vertical NAND strings controlled by SGD-s0. A second sub-block corresponds to those vertical NAND strings controlled by SGD-s1. A third sub-block corresponds to those vertical NAND strings controlled by SGD-s2. A fourth sub-block corresponds to those vertical NAND strings controlled by SGD-s3. A fifth sub-block corresponds to those vertical NAND strings controlled by SGD-s4.

FIG. 4G only shows NAND strings connected to bit line 411. However, a full schematic of the block would show every bit line and five vertical NAND strings (that are in separate sub-blocks) connected to each bit line.

FIG. 4H is a block diagram depicting a top view of another embodiment of a portion of a block of memory cells. As can be seen from FIG. 4H, the block depicted extends in the direction of arrow 550. In one embodiment, the memory array has many layers; however, FIG. 4H only shows the top layer. The block includes a set of Bit Lines connected to vertical columns of the block. Each of the circles representing vertical columns has an “x” to indicate its connection to one bit line. The block of memory cells depicted in FIG. 4H is divided into four sub-blocks 502, 504, 506 and 508. The block depicted in FIG. 4H includes a set of isolation regions 520 and 522, which serve to divide the top layers of block (e.g., the various SGD layers) into sub-blocks, as discussed above. In one embodiment, the isolation regions only divide the layers used to implement select gates so that NAND strings in different sub-blocks can be independently selected. For example, isolation region 520 divides sub-block 502 from sub-block 504 and isolation region 522 divides sub-block 506 from sub-block 508. Line Interconnect LI1, which separates all of the layers (except SL) of sub-block 504 from sub-block 506, is a metal connection to the source line SL from above the memory array. Line Interconnect LI0 is positioned adjacent sub-block 502 and Line Interconnect LI2 is positioned adjacent sub-block 508. In the structure of FIG. 4H, sub-blocks 502 and 504 are on one side of Line Interconnect LI1 and sub-blocks 506 and 508 are on another side of Line Interconnect LI1. Therefore, sub-blocks 502 and 504 are closely connected by the layers WL0-WL239 and sub-blocks 506 and 508 are closely connected by the layers WL0-WL239, while sub-blocks 502 and 504 are separated from sub-blocks 506 and 508 by Line Interconnect LI1. The layers of the block are otherwise the same as described above.

FIG. 4I is a schematic diagram of a portion of the memory array depicted in in FIGS. 4H. FIG. 4I shows physical data word lines WL0-WL239 running across the entire block. The structure of FIG. 4I corresponds to a portion of a block, including bit line 560. Within the block, in one embodiment, each bit line is connected to four NAND strings. Thus, FIG. 4I shows bit line 560 connected to NAND strings 562, 564, 566 and 568. As mentioned above, in one embodiment, SGD0, SGD1 and SGD2 are connected together to operate as a single logical select gate for each sub-block to form SGD-s0, SGD-s1, SGD-s2, and SGD-s3. A first sub-block corresponds to those vertical NAND strings controlled by SGD-s0. A second sub-block corresponds to those vertical NAND strings controlled by SGD-s1. A third sub-block corresponds to those vertical NAND strings controlled by SGD-s2. A fourth sub-block corresponds to those vertical NAND strings controlled by SGD-s3. FIG. 4I only shows NAND strings connected to bit line 560. However, a full schematic of the block would show every bit line and four vertical NAND strings (that are in separate sub-blocks) connected to each bit line.

Although the example memories of FIGS. 4-4I are three dimensional memory structure that includes vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures can also be used with the technology described herein.

The memory systems discussed above can be erased, programmed and read. At the end of a successful programming process, the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. FIG. 5A is a graph of threshold voltage versus number of memory cells, and illustrates example threshold voltage distributions for the memory array when each memory cell stores one bit of data per memory cell. Memory cells that store one bit of data per memory cell data are referred to as single level cells (“SLC”). The data stored in SLC memory cells is referred to as SLC data; therefore, SLC data comprises one bit per memory cell. Data stored as one bit per memory cell is SLC data. FIG. 5A shows two threshold voltage distributions: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Memory cells that have threshold voltages in threshold voltage distribution E are, therefore, in the erased data state (e.g., they are erased). Memory cells that have threshold voltages in threshold voltage distribution P are, therefore, in the programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data “1” and programmed memory cells store data “0.” FIG. 5A depicts read reference voltage Vr. By testing (e.g., performing one or more sense operations) whether the threshold voltage of a given memory cell is above or below Vr, the system can determine a memory cells is erased (state E) or programmed (state P). FIG. 5A also depicts verify reference voltage Vv. In some embodiments, when programming memory cells to data state P, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv.

FIGS. 5B-D illustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”). The data stored in MLC memory cells is referred to as MLC data; therefore, MLC data comprises multiple bits per memory cell. Data stored as multiple bits of data per memory cell is MLC data. In the example embodiment of FIG. 5B, each memory cell stores two bits of data. Other embodiments may use other data capacities per memory cell (e.g., such as three, four, or five bits of data per memory cell).

FIG. 5B shows a first threshold voltage distribution E for erased memory cells. Three threshold voltage distributions A, B and C for programmed memory cells are also depicted. In one embodiment, the threshold voltages in the distribution E are negative and the threshold voltages in distributions A, B and C are positive. Each distinct threshold voltage distribution of FIG. 5B corresponds to predetermined values for the set of data bits. In one embodiment, each bit of data of the two bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP) and an upper page (UP). In other embodiments, all bits of data stored in a memory cell are in a common logical page. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. Table 1 provides an example encoding scheme.

TABLE 1 E A B C LP 1 0 0 1 UP 1 1 0 0

In one embodiment, known as full sequence programming, memory cells can be programmed from the erased data state E directly to any of the programmed data states A, B or C using the process of FIG. 6 (discussed below). For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state E. Then, a programming process is used to program memory cells directly into data states A, B, and/or C. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and/or from data state E to data state C. The arrows of FIG. 5B represent the full sequence programming. In some embodiments, data states A-C can overlap, with memory controller 120 (or control die 211) relying on error correction to identify the correct data being stored.

FIG. 5C depicts example threshold voltage distributions for memory cells where each memory cell stores three bits of data per memory cells (which is another example of MLC data). FIG. 5C shows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) Er represents memory cells that are erased. The other seven threshold voltage distributions (data states) A-G represent memory cells that are programmed and, therefore, are also called programmed states. Each threshold voltage distribution (data state) corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a memory erroneously shifts to its neighboring physical state, only one bit will be affected. Table 2 provides an example of an encoding scheme for embodiments in which each bit of data of the three bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP), middle page (MP) and an upper page (UP).

TABLE 2 Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

FIG. 5C shows seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from memory cells. By testing (e.g., performing sense operations) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine what data state (i.e., A, B, C, D, . . . ) a memory cell is in.

FIG. 5C also shows seven verify reference voltages, VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when programming memory cells to data state A, the system will test whether those memory cells have a threshold voltage greater than or equal to VvA. When programming memory cells to data state B, the system will test whether the memory cells have threshold voltages greater than or equal to VvB. When programming memory cells to data state C, the system will determine whether memory cells have their threshold voltage greater than or equal to VvC. When programming memory cells to data state D, the system will test whether those memory cells have a threshold voltage greater than or equal to VvD. When programming memory cells to data state E, the system will test whether those memory cells have a threshold voltage greater than or equal to VvE. When programming memory cells to data state F, the system will test whether those memory cells have a threshold voltage greater than or equal to VvF. When programming memory cells to data state G, the system will test whether those memory cells have a threshold voltage greater than or equal to VvG. FIG. 5C also shows Vev, which is a voltage level to test whether a memory cell has been properly erased.

In an embodiment that utilizes full sequence programming, memory cells can be programmed from the erased data state Er directly to any of the programmed data states A-G using the process of FIG. 6 (discussed below). For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state Er. Then, a programming process is used to program memory cells directly into data states A, B, C, D, E, F, and/or G. For example, while some memory cells are being programmed from data state Er to data state A, other memory cells are being programmed from data state Er to data state B and/or from data state Er to data state C, and so on. The arrows of FIG. 5C represent the full sequence programming. In some embodiments, data states A-G can overlap, with control die 211 and/or memory controller 120 relying on error correction to identify the correct data being stored. Note that in some embodiments, rather than using full sequence programming, the system can use multi-pass programming processes known in the art.

In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read compare levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG, of FIG. 5C) or verify operation (e.g. see verify target levels VvA, VvB, VvC, VvD, VvE, VvF, and VvG of FIG. 5C) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased).

There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used.

FIG. 5D depicts threshold voltage distributions when each memory cell stores four bits of data, which is another example of MLC data. FIG. 5D depicts that there may be some overlap between the threshold voltage distributions (data states) S0-S15. The overlap may occur due to factors such as memory cells losing charge (and hence dropping in threshold voltage). Program disturb can unintentionally increase the threshold voltage of a memory cell. Likewise, read disturb can unintentionally increase the threshold voltage of a memory cell. Over time, the locations of the threshold voltage distributions may change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. Changing the read reference voltages can help to mitigate such effects. Using ECC during the read process can fix errors and ambiguities. Note that in some embodiments, the threshold voltage distributions for a population of memory cells storing four bits of data per memory cell do not overlap and are separated from each other. The threshold voltage distributions of FIG. 5D will include read reference voltages and verify reference voltages, as discussed above.

When using four bits per memory cell, the memory can be programmed using the full sequence programming discussed above, or multi-pass programming processes known in the art. Each threshold voltage distribution (data state) of FIG. 5D corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. Table 3 provides an example of an encoding scheme for embodiments in which each bit of data of the four bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP), middle page (MP), an upper page (UP) and top page (TP).

TABLE 3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 TP 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 UP 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 MP 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 LP 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1

FIG. 6 is a flowchart describing one embodiment of a process for programming memory cells. For purposes of this document, the term program and programming are synonymous with write and writing. In one example embodiment, the process of FIG. 6 is performed for memory array 202 using the one or more control circuits (e.g., system control logic 260, column control circuitry 210, row control circuitry 220) discussed above. In one example embodiment, the process of FIG. 6 is performed by integrated memory assembly 207 using the one or more control circuits (e.g., system control logic 260, column control circuitry 210, row control circuitry 220) of control die 211 to program memory cells on memory die 201. The process includes multiple loops, each of which includes a program phase and a verify phase. The process of FIG. 6 is performed to implement the full sequence programming, as well as other programming schemes including multi-stage programming. When implementing multi-stage programming, the process of FIG. 6 is used to implement any/each stage of the multi-stage programming process.

Typically, the program voltage applied to the control gates (via a selected data word line) during a program operation is applied as a series of program pulses (e.g., voltage pulses). Between programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step 602 of FIG. 6 , the programming voltage signal (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16V or another suitable level) and a program counter PC maintained by state machine 262 is initialized at 1. In one embodiment, the group of memory cells selected to be programmed (referred to herein as the selected memory cells) are programmed concurrently and are all connected to the same word line (the selected word line). There will likely be other memory cells that are not selected for programming (unselected memory cells) that are also connected to the selected word line. That is, the selected word line will also be connected to memory cells that are supposed to be inhibited from programming. Additionally, as memory cells reach their intended target data state, they will be inhibited from further programming. Those NAND strings (e.g., unselected NAND strings) that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. When a channel has a boosted voltage, the voltage differential between the channel and the word line is not large enough to cause programming. To assist in the boosting, in step 604 the control die will pre-charge channels of NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming. In step 606, NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as “unselected NAND strings.” In one embodiment, the unselected word lines receive one or more boosting voltages (e.g., ˜7-11 volts) to perform boosting schemes. A program inhibit voltage is applied to the bit lines coupled the unselected NAND string.

In step 608, a program voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If a memory cell on a NAND string should be programmed, then the corresponding bit line is biased at a program enable voltage. In step 608, the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently (unless they are inhibited from programming). That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this manner all of the memory cells connected to the selected word line will concurrently have their threshold voltage change, unless they are inhibited from programming.

In step 610, program verify is performed and memory cells that have reached their target states are locked out from further programming by the control die. Step 610 includes performing verification of programming by sensing at one or more verify reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage. In step 610, a memory cell may be locked out after the memory cell has been verified (by a test of the Vt) that the memory cell has reached its target state.

If, in step 612, it is determined that all of the memory cells have reached their target threshold voltages (pass), the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step 614. Otherwise if, in step 612, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 616.

In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distribution are counted. That is, the number of memory cells that have, so far, failed to reach their target state are counted. This counting can be done by state machine 262, memory controller 120, or another circuit. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state.

In step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, then the programming process can stop and a status of “PASS” is reported in step 614. In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 618 is below the number of bits that can be corrected by error correction codes (ECC) during a read process to allow for future/additional errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), then the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria.

If the number of failed memory cells is not less than the predetermined limit, then the programming process continues at step 620 and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 6, 12, 16, 19, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step 624. If the program counter PC is less than the program limit value PL, then the process continues at step 626 during which time the Program Counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size ΔVpgm (e.g., a step size of 0.1-1.0 volts). After step 626, the process loops back to step 604 and another program pulse is applied to the selected word line (by the control die) so that another iteration (steps 604-626) of the programming process of FIG. 6 is performed.

In one embodiment memory cells are erased prior to programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of one or more memory cells from state P to state E of FIG. 5A, from states A/B/C to state E of FIG. 5B, from states A-G to state Er of FIG. 5C or from states S1-S15 to state S0 of FIG. 5D.

One technique to erase memory cells in some memory devices is to bias a p-well (or other types of) substrate to a high voltage to charge up a NAND channel. An erase enable voltage (e.g., a low voltage) is applied to control gates of memory cells while the NAND channel is at a high voltage to erase the non-volatile storage elements (memory cells). Herein, this is referred to as p-well erase.

Another approach to erasing memory cells is to generate gate induced drain leakage (GIDL) current to charge up the NAND string channel. An erase enable voltage is applied to control gates of the memory cells, while maintaining the NAND string channel potential to erase the memory cells. Herein, this is referred to as GIDL erase. Both p-well erase and GIDL erase may be used to lower the threshold voltage (Vt) of memory cells.

In one embodiment, the GIDL current is generated by causing a drain-to-gate voltage at a select transistor (e.g., SGD and/or SGS). A transistor drain-to-gate voltage that generates a GIDL current is referred to herein as a GIDL voltage. The GIDL current may result when the select transistor drain voltage is significantly higher than the select transistor control gate voltage. GIDL current is a result of carrier generation, i.e., electron-hole pair generation due to band-to-band tunneling and/or trap-assisted generation. In one embodiment, GIDL current may result in one type of carriers, e.g., holes, predominantly moving into NAND channel, thereby raising potential of the channel. The other type of carriers, e.g., electrons, are extracted from the channel, in the direction of a bit line or in the direction of a source line, by an electric field. During erase, the holes may tunnel from the channel to a charge storage region of memory cells and recombine with electrons there, to lower the threshold voltage of the memory cells.

The GIDL current may be generated at either end of the NAND string. A first GIDL voltage may be created between two terminals of a select transistor (e.g., drain side select transistor—SGD) that is connected to or near a bit line to generate a first GIDL current. A second GIDL voltage may be created between two terminals of a select transistor (e.g., source side select transistor—SGS) that is connected to or near a source line to generate a second GIDL current. Erasing based on GIDL current at only one end of the NAND string is referred to as a one-sided GIDL erase. Erasing based on GIDL current at both ends of the NAND string is referred to as a two-sided GIDL erase.

FIG. 7 depicts the movement of holes and electrons in a NAND string during a two-sided GIDL erase. An example NAND string 800 that includes a channel 891 connected to a bit line (BL) and to a source line (SL). A tunnel dielectric layer (TNL) 892, charge trapping layer (CTL) 893, and a blocking oxide layer (BOX) 898 are layers which extend around the memory hole of the NAND string (see discussion above). Different regions of the channel layers represent channel regions which are associated with respective storage elements or select gate transistors. These channel regions are at a same height and stack level in the stacked memory device as the control gates of the storage elements or select gate transistors.

An erase voltage Vera is applied to both the bit line (BL) and to the source line (SL). The NAND string 800 includes an SGD transistor 801 with a control gate 806 and a channel region 807. A voltage V_GIDL (e.g., Vera-5v) is applied to the control gate 806 of the SGD transistor 801. The NAND string 800 also includes storage elements 810, 815, 820, and 825, control gates 811, 816, 821, and 826, CTL regions 813, 818, 823, and 828, and channel regions 812, 817, 822, and 827, respectively.

The NAND string 800 includes an SGS transistor 802 with a control gate 856 and a channel region 857. The voltage V_GIDL is applied to the control gate 856 of the SGS transistor 802. The NAND string 800 also includes storage elements 860, 865, 870, and 875, control gates 861, 866, 871, and 876, CTL regions 863, 868, 873, and 878, and channel regions 862, 867, 872, and 877, respectively.

Representative holes are depicted in the channel layers as circles with a “+” sign and representative electrons are depicted in the channel layers as circles with a “−” sign. Electron-hole pairs are generated by a GIDL process. Initially, during an erase operation, the electron-hole pairs are generated at the SGD and SGS transistors. The holes move away from the driven ends into the channel, thereby charging the channel to a positive potential. The electrons generated at the SGD transistor 801 move toward the bit line (BL) due to the positive potential there. The electrons generated at the SGS transistor 802 move toward the source line (SL) due to the positive potential there. Subsequently, during the erase period of each storage element, additional holes are generated by GIDL at virtual junctions which are formed in the channel at the edges of the control gate of the storage element. However, some holes are also removed from the channel as they tunnel to the CTL regions.

Electrons are also generated by the GIDL process. Initially, during the erase operation, the electrons are generated at the SGD and SGS transistors and move toward the driven ends. Subsequently, during the erase period of each storage element, additional electrons are generated by GIDL at virtual junctions, which are formed in the channel at the edges of the control gate of the storage element.

At one end (e.g., drain side) of the NAND string, example electrons 840 and 841 move toward the bit line. Electron 840 is generated at the SGD transistor and electron 841 is generated at a junction of the storage element 815 in the channel region 817. Also, in the drain side, example holes including a hole 842 move away from the bit line as indicated by arrows. The hole 842 is generated at a junction of the storage element 815 in the channel region 817 and can tunnel into the CTL region 818 as indicated by arrow 843.

At the other end (e.g., source side) of the NAND string, example electrons 845 and 849 move toward the source line. Electron 845 is generated at the SGS transistor and electron 849 is generated at a junction of the storage element 865 in the channel region 867. Also, in the source side, example holes including a hole 847 move away from the source line as indicated by the arrow. The hole 847 is generated at a junction of the storage element 865 in the channel region 867 and can tunnel into the CTL region 868 as indicated by arrow 848.

FIG. 8 is a timing diagram describing the signals applied to a block of non-volatile memory (see FIGS. 4-4I) during one embodiment of a two-sided GIDL erase operation. FIGS. 8 and 9 describe a means for erasing the vertical NAND strings by applying a plurality of erase voltage pulses to the plurality of NAND strings via the bit lines and or source lines. FIG. 8 depicts behavior of the following signals: BL, SGD, Dummy WLs, Odd Data WLs, Even Data WLs, SGS and Source. The signal BL is the signal applied to all bit lines for the block being erased. The signal SGD is the signal applied to the gates of all the SGD transistors for all NAND strings of the block. The signal SGS is the signal applied to the gate of all the SGS transistors for all NAND strings of the block. The signal Source is the signal applied to the source line for the block. The signal Dummy WLs is the signal applied to the dummy word lines for the block, which connects to the control gates for all dummy memory cells. The signal Odd Data WLs is the signal applied to all odd data word lines (e.g., WL1, WL3, WL5, . . . ) for all NAND strings of the block. The signal Even Data WLs is the signal applied to all even data word lines (e.g., WL0, WL2, WL4, . . . ) for all NAND strings of the block. The data word lines are connected to the control gates of the data memory cells.

In general, the erase voltage is applied as a series of voltage pulses that increase in magnitude by a step size S (e.g., 0.1-0.3 volts). Between and after the erase voltage pulses, erase verify is performed which include testing to determine whether the NAND strings are successfully erased. For example, between t0 and t1 an erase voltage pulse is applied, between t2 and t3 another erase voltage is applied, between t1 and t2 (between the erase voltage pulses) erase verify is performed, and so on. In one embodiment, all memory cells of all NAND strings are tested at the same time during erase verify. In another embodiment, as depicted in FIG. 8 , memory cells connected to even word lines are tested separately from the testing of memory cells connected to odd word lines.

Between times t0 and t1 an erase voltage pulse is applied to BL and Source. The magnitude of the first erase voltage pulse is Vera (e.g., −21 volts). Also between times t0 and t1, SGD and SGS are raised to a small initial voltage and then to Vera-5 volts to facilitate GIDL generation. In another embodiment, SGD and SGS are raised to an initial voltage and then to Vera-10 volts to facilitate GIDL generation. Also between times t0 and t1, Dummy WLs are set at Vera-5 volts, Odd Data WLs are set at 0.5 volts and Even Data WLs are set at 0.5 volts. The result of applying the erase voltage pulse is that the threshold voltages of the memory cells are lowered.

Between times t1 and t2, the systems perform erase verification. Source remains at ground during erase verify. A voltage VBL (e.g., ˜0.6 volts) is applied to the bit lines BL. FIG. 8 shows two voltage pulses applied to BL between t1 and t2, as one voltage pulse is used to perform erase verify for memory cells connected to even word lines and the other voltage pulse is used to separately perform erase verify for memory cells connected to odd word lines. To facilitate the erase verify, two voltage pulses at Vsg (e.g., 0.3-0.6v) are applied to SGS and SGD and two voltage pulses at Vread (e.g., 8-10 volts) are applied to Dummy WLs. The Even Data WLs and the Odd Data WLs also receive two voltage pulses. First, the Even Data WLs receive a voltage pulse with a magnitude of VCG Vfy (e.g., 0.5 volts), the Odd Data WLs receive a voltage pulse with a magnitude of Vread, and the Dummy WLs receive a voltage pulse with a magnitude of Vread. This causes the memory cells connected to odd word lines to strongly conduct current and the dummy memory cells to strongly conduct current, while testing whether the memory cells connected to the even word lines have a threshold voltage below ˜0.5 volts (or another value demarcating the erased state). Second, the Odd Data WLs receive a voltage pulse with a magnitude of VCG Vfy, the Even Data WLs receive a voltage pulse with a magnitude of Vread, and the Dummy WLs receive a voltage pulse with a magnitude of Vread. This causes the memory cells connected to even word lines to strongly conduct and the dummy memory cells to strongly conduct, while testing whether the memory cells connected to the odd word lines have a threshold voltage below ˜0.5 volts (or another value demarcating the erased state).

During the time period between t2−t3 an additional erase voltage pulse is applied (with step size S indicating the increase in magnitude of the voltage pulse) in the same manner as described above with respect to the time period t0−t1. During the time period between t3−t4 an additional erase verify is performed in the same manner as described above with respect to the time period t1−t2. The process depicted in FIG. 8 continue with additional erase voltage pulses and additional erase verify until all or enough memory cells (or NAND strings) pass erase verify. More details are described below.

As mentioned above, defects in a non-volatile memory, such as a short or leak between a word line and a memory hole (e.g., a short or leak between a word line and the channel of a NAND string) can introduce an error into the data being stored. Sometimes such a defect does not appear until after the non-volatile memory has been in use. To prevent failures of the non-volatile memory when in use due to defects that first present during operation by a user, manufacturers of non-volatile memory may include various processes for testing the memory in an effort to detect defects before the non-volatile memory is used to store new hist/user data. One test for a leak between a word line and memory hole includes causing all memory cells of a set of NAND strings to be in a common threshold voltage distribution (e.g., in the erased state), performing sensing operations to test whether the memory cells are actually in the common threshold voltage distribution separately for memory cells connected to even word line and memory cells connected to odd word lines, and determining whether the results of the sensing for even word lines matches the sensing for odd word lines. If the results of the sensing for even word lines does not match the sensing for odd word lines, then there may be a short or leak between a word line and a memory hole.

The above-described test for a leak between a word line and memory hole requires multiple sensing operations, which takes time and may impact system performance. Therefore, it is proposed to conduct the test during the erase process. Rather than perform multiple additional sensing operations for the test, the results of the already performed erase verify process can be used so that no new sensing is required and no significant degrading in memory system performance is experienced.

FIG. 9 is a flow chart describing one embodiment of a process for erasing non-volatile memory that includes testing for a defect (e.g., a leak between a word line and memory hole) without performing additional sensing operations that would slow down the erase process (or otherwise materially degrade system performance). In one example implementation, the process of FIG. 9 utilizes the two sided GIDL erase described by FIGS. 7 and 8 . The process of FIG. 9 can be performed by any one of the one or more control circuits discussed above. For example, the process of FIG. 9 can be performed entirely by the memory die 200 (see FIG. 2A) or by an integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In on example, the process of FIG. 9 is performed by or at the direction of state machine 262, using other components of System Control Logic 260, Column Control Circuitry 210 And Row Control Circuitry 220. In another embodiment, the process of FIG. 9 is performed by or at the direction of memory controller 120. In one embodiment, the erasing of FIG. 9 is performed on a block of memory cells, the block is divided into sub-blocks, and each sub-block comprises many NAND stings, as discussed above.

In step 902 of FIG. 9 , the control circuit concurrently erases the NAND strings of the multiple sub-blocks. In one embodiment, the control circuit applies doses of an erase signal to the block of memory cells (e.g., applying a series of erase voltage pulses to the plurality of bit lines and/or source line for a block of NAND strings) such that all of the NAND strings of the block experience erasing (e.g., changing/lowering of threshold voltage, or another property, of the memory cells). In step 904, the control circuit performs an erase verify process for the NAND strings of the multiple sub-blocks including separately performing erase verify for memory cells connected to even word lines to generate an even result for each NAND string and performing erase verify for memory cells connected to odd word lines to generate an odd result for each NAND string. For example, the system can perform the erase verify process depicted in FIG. 8 . In one embodiment, erase verify is performed for an entire block (or other grouping) of memory cells. In another embodiment, erase verify is performed separately for each sub-block (e.g., first perform erase verify for sub-block 0, then perform erase verify for sub-block 1, then perform erase verify for sub-block 2, . . . ). FIG. 8 shows two pulses applied to the bit lines and word lines during erase verify; however, if erase verify is performed separately for each sub-block then two pulses will be applied to the bit lines and word lines for each sub-block. In one embodiment, the control circuit is configured to perform an erase verify process for the NAND strings of the multiple sub-blocks by, separately for each sub-block, performing erase verify for the NAND strings of the sub-block between and after the doses of the erase signal including separately performing erase verify for memory cells connected to even word lines to generate the even result for each NAND string and performing erase verify for memory cells connected to odd word lines to generate the odd result for each NAND string.

In step 906, the control circuit determines that the erasing of the memory cells for a first sub-block of the multiple sub-blocks erase verified successfully when a sum of NAND strings of the first sub-block that failed the erase verify process for memory cells connected to even word lines or failed the erase verify process for memory cells connected to odd word lines is below a first threshold. In some embodiments, the first threshold is greater than zero because the system may tolerate some errors in the erase process since the memory system's error correction capability can correct these errors. In one embodiment, the control circuit is configured to, separately for each sub-block, determine that erasing of the memory cells for the respective sub-block erase verified successfully when a sum of NAND strings that failed erase verify for memory cells connected to even word lines or failed erase verify for memory cells connected to odd word lines is below the first threshold.

In step 908, the control circuit determines that the erasing of the first sub-block failed, despite determining that the memory cells for the first sub-block erase verified successfully if a number of NAND strings of the first sub-block that have the even result different than the odd result is greater than a second threshold (e.g., the first threshold is higher than the second threshold). In one embodiment, the control circuit is configured to determine that the erasing of the first sub-block failed by, for multiple NAND strings of the first sub-block, comparing a last even result for the NAND string to a last odd result for the NAND string and determining that the erasing of the first sub-block failed if a number of NAND strings of the first sub-block that have the last even result different than the last odd result is greater than the second threshold. The last even result is the even result used to determine that the respective NAND string erased verified successfully and was obtained prior to determining that erasing of the memory cells for the first sub-block erase verified successfully. The last odd result is the odd result used to determine that the NAND string erased verified successfully and was obtained prior to determining that erasing of the memory cells for the first sub-block erase verified successfully.

In step 910, the control circuit determines that the erasing of one or more additional sub-blocks of the multiple sub-blocks of the block failed based on and in response to determining that the erasing of the first sub-block failed. In one embodiment, the control circuit is configured to determine that the erasing of all sub-blocks of the multiple sub-blocks failed (and all sub-blocks of the block have a defect) based on and in response to determining that the erasing of the first sub-block failed.

In one embodiment, the block comprises five sub-blocks (see e.g., FIG. 4B) connected together by the plurality of word lines, the five sub-blocks include the first sub-block (e.g., 430) and four additional sub-blocks (e.g., 440, 450, 460, 470), and the control circuit is configured to determine that the erasing of all five sub-blocks of the multiple sub-blocks failed based on and in response to determining that the erasing of the first sub-block 430 failed without determining whether a number of NAND strings of the four additional sub-blocks (e.g., 440, 450, 460, 470) that have the last even result different than the last odd result is greater than the second threshold.

In one embodiment, the block comprises four sub-blocks (e.g., see 502-508 of FIG. 4H) including the first sub-block 502, a second sub-block 504, a third sub-block 506 and a fourth sub-block 508. The first sub-block is connected to the second sub-block (e.g., see sub-blocks 502 and 504 of FIG. 4H, which are only separated by an isolation region rather than being separated by a Line Interconnect), the third sub-block is connected to the fourth sub-block (e.g., see sub-blocks 506 and 508 of FIG. 4H, only separated by an isolation region rather than being separated by a Line Interconnect), and the control circuit is configured to determine that the erasing of the second sub-block failed without determine that the erasing of the third sub-block and fourth sub-block failed, based on and in response to determining that the erasing of the first sub-block failed. In addition, the control circuit is configured to determine that the erasing of the third sub-block failed and the erasing of the fourth sub-block failed, despite determining that erasing of the memory cells for the third sub-block erase verified successfully, if the number of NAND strings of the third sub-block that have the even result different than the odd result is greater than the second threshold.

In one embodiment, the control circuit is configured to determine that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed without testing whether a number of NAND strings of the one or more additional sub-blocks that have an even result different than an odd result is greater than the second threshold.

In one embodiment, the control circuit is configured to determine that the erasing of the memory cells for a first sub-block of the multiple sub-blocks erase verified successfully if the sum of the number of NAND strings that failed erase verify for memory cells connected to even word lines or failed erase verify for memory cells connected to odd word lines is greater the second threshold and less than the first threshold.

In step 912, the control circuit determines that the first sub-block and the one or more additional sub-blocks are defective in response to determining that the erasing of the first sub-block failed (without testing whether a number of NAND strings of the one or more additional sub-blocks that have an even result different than an odd result is greater than the second threshold). In step 914, the control circuit retires the first sub-block and the one or more additional sub-blocks in response to determining that the first sub-block and the one or more additional sub-blocks are defective. In step 916, the control circuit continues using other sub-blocks of the block to store host data after retiring the first sub-block and the one or more additional sub-blocks. In an alternative embodiment, the control circuit will retire the entire block if any sub-block is found to be defective.

In one set of embodiments, the first threshold is higher than the second threshold. For example, the first threshold may be 56 bits per 1000 bits and the second threshold may be 16 bits per 1000 bits. Alternatively, the system may conclude that the erase process was successful, or at least that the erase verify process indicated that the erase process was successful, if no more than 5.6% of the NAND strings failed to erase verify. However, when performing the test for defects in steps 908 and 910, the system will conclude that a defect exists (and erasing failed) if there is a mismatch between even and odd results for 1.6% of NAND strings. Note that other values can be used for the first threshold and the second threshold.

FIG. 10 is a flow chart describing one embodiment of a process for erasing non-volatile memory that includes testing for a defect (e.g., a leak between a word line and memory hole) without performing additional sensing operations that would slow down the erase process (or otherwise materially degrade system performance). In one example implementation, the process of FIG. 10 utilizes the two sided GIDL erase described by FIGS. 7 and 8 . The process of FIG. 10 can be performed by any one of the one or more control circuits discussed above. For example, the process of FIG. 10 can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In on example, the process of FIG. 10 is performed by or at the direction of state machine 262, using other components of System Control Logic 260, Column Control Circuitry 210 And Row Control Circuitry 220. In another embodiment, the process of FIG. 10 is performed by or at the direction of memory controller 120. In one embodiment, the process of FIG. 10 is an example implementation of the process of FIG. 9 .

In step 1002 of FIG. 10 , the control circuit erases multiple sub-blocks of the block by applying a plurality of erase voltage pulses to the NAND strings of the multiple sub-blocks. In step 1004, the control circuit separately, for each sub-block, performs an erase verify process for the NAND strings of the respective sub-block including separately performing erase verify for memory cells connected to even word lines to generate an even result for each NAND string and for memory cells connected to odd word lines to generate an odd result for each NAND string. In step 1006, the control circuit determines that erasing of the memory cells for a first sub-block of the multiple sub-blocks erase verified successfully because a sum of NAND strings of the first sub-block that failed the erase verify process for memory cells connected to even word lines or failed the erase verify process for memory cells connected to odd word lines is below a first threshold. In step 1008, the control circuit determines that the erasing of the first sub-block failed, despite determining that erasing of the memory cells for the first sub-block erase verified successfully, because a number of NAND strings of the first sub-block that have the even result different than the odd result is greater than a second threshold. Because the erasing of the first sub-block failed, the control circuit concludes that the first sub-block has a defect. In step 1010, the control circuit determines that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed, and that the one or more additional sub-blocks have a defect, based on and in response to determining that the erasing of the first sub-block failed. In step 1012, the control circuit retires the first sub-block and the one or more additional sub-blocks in response to determining that the first sub-block and the one or more additional sub-blocks have a defect. In step 1014 the control circuit continues using other sub-blocks of the block to store host data after retiring the first sub-block and the one or more additional sub-blocks. In an alternative embodiment, the control circuit will retire the entire block if any sub-block is found to be defective.

FIG. 11 is a flow chart describing one embodiment of a process for erasing non-volatile memory that includes testing for a defect (e.g., a leak between a word line and memory hole) without performing additional sensing operations that would slow down the erase process (or otherwise materially degrade system performance). In one example implementation, the process of FIG. 11 utilizes the two sided GIDL erase described by FIGS. 7 and 8 . The process of FIG. 11 can be performed by any one of the one or more control circuits discussed above. For example, the process of FIG. 11 can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In on example, the process of FIG. 11 is performed by or at the direction of state machine 262, using other components of System Control Logic 260, Column Control Circuitry 210 And Row Control Circuitry 220. In another embodiment, the process of FIG. 11 is performed by or at the direction of memory controller 120. In one embodiment, the process of FIG. 11 is an example implementation of the process of FIG. 9 . In one embodiment, the process of FIG. 11 is an example implementation of the process of FIG. 10 . In one embodiment, the process of erasing is performed on a block of memory cells. That is, in one embodiment a block is the unit of erase. Thus, the processes of FIGS. 9-11 are performed on a block. In one example, the process of FIG. 11 is performed for the embodiment of FIG. 4B.

In step 1102, the magnitude of the initial erase voltage pulse (Vera) is set. One example of an initial magnitude is 21 volts. However, other initial magnitudes can also be used. In step 1104, the erase voltage pulse is applied to the set of NAND strings. In one embodiment the erase voltage pulse is applied to the bit lines. In another embodiment the erase voltage is applied to the source line. In another embodiment the erase voltage pulse is applied to the bit lines and the source line. Step 1104 corresponds to the time period between t0 and t1 of FIG. 8 .

In step 1106, erase verify is performed separately for each sub-block of the block being erased. For example, in an embodiment with five sub-blocks (e.g., sub-blocks 430, 440, 450, 460 and 470 of FIG. 4B), first step 1106 is performed for sub-block 430, subsequently step 1106 is performed for sub-block 440, subsequently step 1106 is performed for sub-block 450, subsequently step 1106 is performed for sub-block 460, and finally step 1106 is performed for sub-block 470. When performing erase verify for a sub-block, erase verify for memory cells connected to even word lines is performed separately from performing erase verify for memory cells connected to odd word lines. That is, the control circuit will perform erase verify for those memory cells connected to even word lines while not performing erase verify for memory cells connected to odd word lines. Subsequently, the control circuit will perform erase verify for those memory cells connected to odd word lines while not performing erase verify for memory cells connected to even word lines. Step 1106 corresponds to the timeframe between t1 and t2 of FIG. 8 . When performing erase verify for memory cells connected to even word lines, the even word lines will receive VCG Vfy and odd word lines will receive Vread. The control circuit will sense the NAND strings (e.g., using the sense amplifiers) to determine if sufficient current is flowing. When performing erase verify for memory cells connected to odd word lines, the odd word lines will receive VCG Vfy and even word lines will receive Vread. The control circuit will again sense the NAND strings to determine if sufficient current is flowing.

When the NAND string has completed erasing, the erase verify for the memory cells connected to even word line should show a successful erase verify and the erase verify for memory cells connected to the odd word lines should show a successful erase verify. In step 1008, the results from the erase verify from memory cells connected to even word lines will be compared to the results from memory cells connected to odd word lines for each NAND string of the first sub-block, referred to as sub-block 0 (e.g., sub-block 430 of FIG. 4B). Step 1108 can be performed as part of the erase verify during step 1106 for sub-block 0.

In step 1110, the control circuit determines the status of the erase verify (from step 1006). If all of the NAND strings passed erase verify for odd word lines and erase verify for even word lines, then the process will continue at step 1020. If the number of NAND strings that have failed either erase verify for even word lines or erase verify for odd word lines is less than the first threshold then the control circuit will consider the verification process to have passed and the process will also continue in step 1120. If the number of NAND strings that have failed either erase verify for even word lines or erase verify for odd word lines is greater than the first threshold, then the process will continue with step 1112.

In step 1112, the control circuit determines whether the number of erase voltage pulses is greater than a predetermined limit. In one example, the predetermined limit is six pulses. In another example, the predetermined limit is 20 pulses. Other examples of predetermined limits can also be used. If the number of pulses is less than or equal to the predetermined limit, then the control circuit will perform another iteration of the erase process (e.g., steps 1104-1112), which includes applying another erase voltage pulse. Thus, the process will continue at step 1114 to increase the magnitude of the next erase voltage pulse and then the process will loop back to step 1104 to apply the next erase voltage pulse. If, in step 1112, it is determined that the number of erase voltage pulses already applied in the current erase process is greater than the predetermined limit, then the erase process failed (step 1116) and the current block being erased is retired from any further use by the memory system.

If it is determined that the erase verify process indicated that the block of memory cells verified successfully because less than the first threshold number of NAND strings failed erase verify for all sub-blocks (step 1110), then in step 1120 the control circuit determines the number of NAND strings of sub-block 0 that had the last even result different than the last odd result. In the discussion above, each time that the control circuit performed erase verify for sub-block 0 in step 1106 it also compared the even result to the odd result for each of NAND strings of sub-block 0. The even result and the odd result from the last time that steps 1106-1108 were performed prior to step 1110 concluding that erase verify was successful is referred to as last even result different and the last odd result. In one embodiment, when performing steps 1106 and 1108, the even result for each NAND string is stored in a first latch (e.g., BDL of FIG. 3 ) for the sense amplifier connected to that NAND string, the odd result for each NAND string is stored in a second latch (e.g., CDL), and a third latch (e.g., TDL) stores the result of the comparison from step 1108. In an embodiment where the comparison is XOR, then 0 is stored in the third latch if the even result for a NAND string matches the odd result for the NAND string, and 1 is stored in the third latch if the even result for a NAND string does not match the odd result for the NAND string; thereby, allowing step 1120 to include counting the number of third latches that store 1.

If the number of NAND strings of sub-block 0 that have a last even result different than a last odd result is not greater than the second threshold (TH2) in step 1122, then the control circuit concludes that the erasing of the entire block (including all sub-blocks of the block) was successful. If the number of NAND strings of sub-block 0 that have a last even result different than a last odd result is greater than the second threshold (TH2) in step 1122, then the control circuit concludes that erasing of sub-block 0 failed (despite determining that the memory cells for the sub-block 0 erase verified successfully in step 1110) and that sub-block 0 has a defect (step 1130). In step 1132, the control circuit determines that the erasing of all sub-blocks of the block being erase failed (all sub-blocks of the block being erased have a defect) based on and in response to determining that the erasing of the sub-block 0 failed. For example, in the embodiment of FIG. 4B all of the sub-blocks are connected by the word line layer WL0-WL239, and determining that sub-block 430 failed results in a conclusion that sub-blocks 440-470 also failed. Because the sub-blocks of the block depicted in FIG. 4B are only separated at the select gate layers by isolation regions 482, 484, 486 and 488, a defect in one sub-block is an indication of a defect in all sub-blocks. Therefore, only testing sub-block 0 (sub-block 430) saves time. Although in the embodiment above, sub-block 0 serves as the representative sub-block for test, in other embodiments other sub-blocks can be the representative sub-block for test.

In an alternative embodiment, step 1108 includes comparing the results from the erase verify for memory cells connected to even word lines to the results for memory cells connected to odd word lines for each NAND string of the sub-block 0 (e.g., sub-block 430), sub-block 1 (e.g., sub-block 440) and sub-block 2 (e.g., sub-block 450). Steps 1120 and 1122 include determining whether the number of NAND strings for sub-block 0 (e.g., sub-block 430) that have a last even result different than a last odd result is greater the second threshold, determining whether the number of NAND strings for sub-block 1 (e.g., sub-block 440) that have a last even result different than a last odd result is greater the second threshold, and determining whether the number of NAND strings for sub-block 2 (e.g., sub-block 450) that have a last even result different than a last odd result is greater the second threshold. If the number of NAND strings for sub-block 0 (e.g., sub-block 430) that have a last even result different than a last odd result is greater the second threshold, then the control circuit concludes that sub-block 0 (e.g., sub-block 430) and the sub-block 4 (e.g., sub-block 470) failed the erase process, have a defect and should be retired from further use. If the number of NAND strings for sub-block 1 (e.g., sub-block 440) that have a last even result different than a last odd result is greater the second threshold, then the control circuit concludes that sub-block 1 (e.g., sub-block 440) and the sub-block 3 (e.g., sub-block 460) failed the erase process, have a defect and should be retired from further use. If the number of NAND strings for sub-block 2 (e.g., sub-block 450) that have a last even result different than a last odd result is greater the second threshold, then the control circuit concludes that sub-block 2 (e.g., sub-block 450) failed the erase process, has a defect and should be retired from further use.

FIGS. 12A and 12B together are a flow chart describing one embodiment of a process for erasing non-volatile memory that includes testing for a defect (e.g., a leak between a word line and memory hole) without performing additional sensing operations that would slow down the erase process (or otherwise materially degrade system performance). In one example implementation, the process of FIGS. 12A and 12B utilizes the two sided GIDL erase described by FIGS. 7 and 8 . The process of FIGS. 12A and 123B can be performed by any one of the one or more control circuits discussed above. For example, the process of FIGS. 12A and 12B can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In on example, the process of FIGS. 12A and 12B is performed by or at the direction of state machine 262, using other components of System Control Logic 260, Column Control Circuitry 210 And Row Control Circuitry 220. In another embodiment, the process of FIGS. 12A and 12B is performed by or at the direction of memory controller 120. In one embodiment, the process of FIGS. 12A and 12B is an example implementation of the process of FIG. 9 . In one embodiment, the process of FIGS. 12A and 12B is an example implementation of the process of FIG. 10 . In one example, the process of FIGS. 12A and 12B is performed for the embodiment of FIG. 4H.

Steps 1202, 1204 and 1206 of FIG. 12 are the same as steps 1102, 1104 and 1106 of FIG. 11 . Step 1208 a of FIG. 12 is the same as step 1108 of FIG. 11 . Thus, in step 1208 a, the results from the erase verify for memory cells connected to even word lines will be compared to the results for memory cells connected to odd word lines for each NAND string of sub-block 0 (e.g., sub-block 502 of FIG. 4H). In step 1208 b, the results from the erase verify for memory cells connected to even word lines will be compared to the results for memory cells connected to odd word lines for each NAND string of sub-block 2 (e.g., sub-block 506 of FIG. 4H). If it is determined that the erase verify process indicated that the block of memory cells verified successfully because less than the first threshold number of NAND strings failed erase verify for all sub-blocks (step 1210), then the process continues at steps 1250 and 1252 of FIG. 12B. If the number of NAND strings that have failed either erase verify for even word lines or erase verify for odd word lines is greater than the first threshold, then the process will continue with step 1212. Steps 1212, 1214 and 1216 of FIG. 12 are the same as steps 1112, 1114 and 1116 of FIG. 11 . Thus, if the predetermined limit on number of erase pulses has not been met, then another loop/iteration of steps 1204-1214 are performed.

In step 1250 of FIG. 12 , the control circuit determines the number of NAND strings of sub-block 0 (e.g., sub-block 502 of FIG. 4H) that had the last even result different than the last odd result. In one embodiment, the even result for each NAND string is stored in a first latch (e.g., BDL of FIG. 3 ) for the sense amplifier connected to that NAND string, the odd result for each NAND string is stored in a second latch (e.g., CDL), and a third latch (e.g., TDL) stores the result of the comparison from step 1208 a.

If the number of NAND strings of sub-block 0 that have a last even result different than a last odd result is not greater than the second threshold (TH2) in step 1260, then the control circuit concludes that the erasing of the sub-blocks 0 (e.g. sub-block 502 of FIG. 4H) and sub-block 1 (e.g., sub-block 504) was successful. If the number of NAND strings of sub-block 0 that have the last even result different than the last odd result is greater than the second threshold (TH2) in step 1260, then the control circuit concludes that erasing of sub-block 0 failed (despite determining that the memory cells for the sub-block 0 erase verified successfully in step 1210) and that sub-block 0 has a defect (step 1264). In step 1266, the control circuit determines that the erasing of sub-block 1 (e.g., sub-block 504) of the block being erase also failed and has a defect based on and in response to determining that the erasing of the sub-block 0 failed. For example, in the embodiment of FIG. 4H, sub-blocks 502 and 504 are connected by the word line layer WL0-WL239, and determining that sub-block 502 failed results in a conclusion that sub-block 504 also failed (and both have defects). Because the sub-blocks 502 and 504 are only separated at the select gate layers by isolation region 520, a defect in one sub-block 502 is an indication of a defect sub-block 504. Therefore, only testing sub-block 0 saves time. Although in the embodiment above, sub-block 502 serves as the representative sub-block for test, in other embodiments sub-block 504 can be the representative sub-block for test.

In step 1252 of FIG. 12 , the control circuit determines the number of NAND strings of sub-block 2 (e.g., sub-block 506 of FIG. 4H) that had the last even result different than the last odd result. In one embodiment, the even result for each NAND string is stored in a first latch (e.g., BDL of FIG. 3 ) for the sense amplifier connected to that NAND string, the odd result for each NAND string is stored in a second latch (e.g., CDL), and a third latch (e.g., TDL) stores the result of the comparison from step 1208 b.

If the number of NAND strings of sub-block 2 that have a last even result different than a last odd result is not greater than the second threshold (TH2) in step 1270, then the control circuit concludes that the erasing of the sub-block 2 (e.g. sub-block 506 of FIG. 4H) and sub-block 3 (e.g., sub-block 508) was successful (1272). If the number of NAND strings of sub-block 2 that have a last even result different than a last odd result is greater than the second threshold (TH2) in step 1270, then the control circuit concludes that erasing of sub-block 2 failed (despite determining that the memory cells for the sub-block 2 erase verified successfully in step 1210) and that sub-block 2 has a defect (step 1274). In step 1276, the control circuit determines that the erasing of sub-block 3 (e.g., sub-block 508) of the block being erased also failed and has a defect based on and in response to determining that the erasing of the sub-block 2 failed. For example, in the embodiment of FIG. 4H, sub-blocks 506 and 508 are connected by the word line layer WL0-WL239, and determining that sub-block 506 failed results in a conclusion that sub-block 508 also failed. Because the sub-blocks 506 and 508 are only separated at the select gate layers by isolation region 522, a defect in sub-block 506 is indicative of a defect in sub-block 508. Therefore, only testing sub-block 2 saves time. Although in the embodiment above, sub-block 2 serves as the representative sub-block for test, in other embodiments sub-block 3 can be the representative sub-block for test.

Note that a defect in sub-block 502 of FIG. 4H may not be indicative of a defect in sub-blocks 506 and 508, as sub-block 502 is separated from sub-blocks 506 and 508 by Line Interconnect LI1.

In one embodiment, steps 1250, 1260, 1262, 1264, 1266 are performed in parallel with steps 1252, 1270, 1272, 1274 and 1276.

After the processes of FIG. 11 or 12A/B are performed, the defective sub-blocks are retired from further use (e.g., no longer storing host/user data) while other sub-blocks of the same block can continue to be used.

A system has been described that includes testing for a defect (e.g., a leak between a word line and memory hole) while erasing non-volatile memory without performing additional sensing operations that would slow down the erase process (or otherwise materially degrade system performance).

One embodiment includes a non-volatile storage apparatus, comprising: a plurality of word lines; a block of non-volatile memory cells comprising multiple sub-blocks, each sub-block includes NAND strings connected to the plurality of word lines; and a control circuit connected to the block of non-volatile memory cells and the plurality of word lines. The control circuit is configured to: concurrently erase the NAND strings of the multiple sub-blocks, perform an erase verify process for the NAND strings of the multiple sub-blocks including separately performing erase verify for memory cells connected to even word lines to generate an even result for each NAND string and performing erase verify for memory cells connected to odd word lines to generate an odd result for each NAND string, determine that the erasing of the memory cells for a first sub-block of the multiple sub-blocks erase verified successfully when a sum of NAND strings of the first sub-block that failed the erase verify process for memory cells connected to even word lines or failed the erase verify process for memory cells connected to odd word lines is below a first threshold, determine that the erasing of the first sub-block failed, despite determining that the memory cells for the first sub-block erase verified successfully, if a number of NAND strings of the first sub-block that have the even result different than the odd result is greater than a second threshold, and determine that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed based on and in response to determining that the erasing of the first sub-block failed.

One embodiment includes a method of operating non-volatile storage. The non-volatile storage includes a block of non-volatile memory cells arranged in NAND strings. The block is divided into sub-blocks. The method comprises: erasing multiple sub-blocks of the block by applying a plurality of erase voltage pulses to the NAND strings of the multiple sub-blocks; separately, for each sub-block, performing an erase verify process for the NAND strings of the respective sub-block including separately performing erase verify for memory cells connected to even word lines to generate an even result for each NAND string and for memory cells connected to odd word lines to generate an odd result for each NAND string; determining that erasing of the memory cells for a first sub-block of the multiple sub-blocks erase verified successfully because a sum of NAND strings of the first sub-block that failed the erase verify process for memory cells connected to even word lines or failed the erase verify process for memory cells connected to odd word lines is below a first threshold; determining that the erasing of the first sub-block failed, despite determining that erasing of the memory cells for the first sub-block erase verified successfully, because a number of NAND strings of the first sub-block that have the even result different than the odd result is greater than a second threshold; and determining that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed based on and in response to determining that the erasing of the first sub-block failed.

In one example implementation, the block includes five sub-blocks including the first sub-block, a second sub-block, a third sub-block, a fourth sub-block and a fifth sub-block; and the determining that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed comprises determining that the erasing of the first sub-block, the second sub-block, the third sub-block, the fourth sub-block and the fifth sub-block all failed based on and in response to determining that the erasing of the first sub-block failed.

In one example implementation, the block includes four sub-blocks including the first sub-block, a second sub-block, a third sub-block, and a fourth sub-block. The method further comprises: determining that the erasing of the third sub-block failed; and determining that the erasing of the fourth sub-block failed based on and in response to determining that the erasing of the third sub-block failed, the determining that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed comprises determining that the erasing of the second sub-block failed based on and in response to determining that the erasing of the first sub-block failed.

One embodiment includes a non-volatile storage apparatus, comprising: a block of non-volatile memory cells comprising multiple sub-blocks, each sub-block includes NAND strings connected to a same plurality of word lines; and a control circuit connected to the block of non-volatile memory cells. The control circuit is configured to: apply doses of an erase signal (e.g., erase voltage pulses) to the block of memory cells; separately for each sub-block, perform erase verify for the NAND strings of the sub-block between and after the doses of the erase signal including separately performing erase verify for memory cells connected to even word lines to generate an even result and performing erase verify for memory cells connected to odd word lines to generate an odd result; separately for each sub-block, determine that erasing of the memory cells for the respective sub-block erase verified successfully when a sum of NAND strings that failed erase verify for memory cells connected to even word lines or failed erase verify for memory cells connected to odd word lines is below a first threshold; for multiple NAND strings of one sub-block of the multiple sub-blocks, compare a last even result for the respective NAND string to a last odd result for the respective NAND string, the last even result is the even result used to determine that the respective NAND strings erased verified successfully and was obtained prior to determining that erasing of the memory cells for the respective sub-block erase verified successfully, the last odd result is the odd result used to determine that the NAND string erased verified successfully and was obtained prior to determining that erasing of the memory cells for the respective sub-block erase verified successfully; determine that the erasing of the one sub-block failed, despite determining that erasing of the memory cells for the respective sub-block erase verified successfully, if a number of NAND strings of the one sub-block that have the last even result different than the last odd result is greater than a second threshold; and determine that the erasing of an additional sub-block of the multiple sub-blocks failed based on and in response to determining that the erasing of the one sub-block failed without determining whether a number of NAND strings of the additional sub-block that have the last even result different than the last odd result is greater than the second threshold.

For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.

For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via one or more intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.

For purposes of this document, the term “based on” may be read as “based at least in part on.”

For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.

For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto. 

What is claimed is:
 1. A non-volatile storage apparatus, comprising: a plurality of word lines; a block of non-volatile memory cells comprising multiple sub-blocks, each sub-block includes NAND strings connected to the plurality of word lines; and a control circuit connected to the block of non-volatile memory cells and the plurality of word lines, the control circuit is configured to: concurrently erase the NAND strings of the multiple sub-blocks, perform an erase verify process for the NAND strings of the multiple sub-blocks including separately performing erase verify for memory cells connected to even word lines to generate an even result for each NAND string and performing erase verify for memory cells connected to odd word lines to generate an odd result for each NAND string, determine that the erasing of the memory cells for a first sub-block of the multiple sub-blocks erase verified successfully when a sum of NAND strings of the first sub-block that failed the erase verify process for memory cells connected to even word lines or failed the erase verify process for memory cells connected to odd word lines is below a first threshold, determine that the erasing of the first sub-block failed, despite determining that the memory cells for the first sub-block erase verified successfully, if a number of NAND strings of the first sub-block that have the even result different than the odd result is greater than a second threshold, and determine that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed based on and in response to determining that the erasing of the first sub-block failed.
 2. The non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to determine that the erasing of all sub-blocks of the multiple sub-blocks failed based on and in response to determining that the erasing of the first sub-block failed.
 3. The non-volatile storage apparatus of claim 1, wherein: the block comprises five sub-blocks connected together by the plurality of word lines, the five sub-block include the first sub-block and four additional sub-blocks; and the control circuit is configured to determine that the erasing of all five sub-blocks of the multiple sub-blocks failed based on and in response to determining that the erasing of the first sub-block failed without determining whether a number of NAND strings of the four additional sub-blocks that have the last even result different than the last odd result is greater than the second threshold.
 4. The non-volatile storage apparatus of claim 1, wherein: the block comprises four sub-blocks including the first sub-block, a second sub-block, a third sub-block and a fourth sub-block; the first sub-block is connected to the second sub-block; the third sub-block is connected to the fourth sub-block; and the control circuit is configured to determine that the erasing of the second sub-block failed, without determine that the erasing of the third sub-block and fourth sub-block failed, based on and in response to determining that the erasing of the first sub-block failed.
 5. The non-volatile storage apparatus of claim 4, wherein: the control circuit is configured to determine that the erasing of the third sub-block failed and the erasing of the fourth sub-block failed, despite determining that erasing of the memory cells for the third sub-block erase verified successfully, if the number of NAND strings of the third sub-block that have the even result different than the odd result is greater than the second threshold.
 6. The non-volatile storage apparatus of claim 4, wherein: the control circuit is configured to determine that the erasing of the first sub-block failed and the erasing of one or more additional sub-blocks of the multiple sub-blocks failed, without determining that number of NAND strings of the one or more additional sub-blocks have a number of even results different than odd results by more than the second threshold.
 7. The non-volatile storage apparatus of claim 1, wherein: the first threshold is higher than the second threshold.
 8. The non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to determine that the erasing of the memory cells for a first sub-block of the multiple sub-blocks erase verified successfully if the sum of the number of NAND strings that failed erase verify for memory cells connected to even word lines or failed erase verify for memory cells connected to odd word lines is greater the second threshold and less than the first threshold.
 9. The non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to determine that the block is defective and retire the block in response to determining that the erasing of the first sub-block failed.
 10. The non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to determine that the first sub-block and the one or more additional sub-blocks are defective in response to determining that the erasing of the first sub-block failed; the control circuit is configured to retire the first sub-block and the one or more additional sub-blocks in response to determining that the first sub-block and the one or more additional sub-blocks are defective; and the control circuit is configured to continue using other sub-blocks of the block to store host data after retiring the first sub-block and the one or more additional sub-blocks.
 11. The non-volatile storage apparatus of claim 1, further comprising: a plurality of bit lines, each bit line is connected to one NAND string in each sub-block, the control circuit is configured to concurrently erase the NAND strings of the multiple sub-blocks by applying a series of voltage pulses to the plurality of bit lines.
 12. The non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to determine that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed without testing whether a number of NAND strings of the one or more additional sub-blocks that have an even result different than an odd result is greater than the second threshold.
 13. The non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to concurrently erase the NAND strings of the multiple sub-blocks by applying doses of an erase signal to the block of memory cells; the control circuit is configured to perform an erase verify process for the NAND strings of the multiple sub-blocks by, separately for each sub-block, performing erase verify for the NAND strings of the sub-block between and after the doses of the erase signal including separately performing erase verify for memory cells connected to even word lines to generate the even result for each NAND string and performing erase verify for memory cells connected to odd word lines to generate the odd result for each NAND string; the control circuit is configured to, separately for each sub-block, determine that erasing of the memory cells for the respective sub-block erase verified successfully when a sum of NAND strings that failed erase verify for memory cells connected to even word lines or failed erase verify for memory cells connected to odd word lines is below the first threshold; and the control circuit is configured to determine that the erasing of the first sub-block failed by: for multiple NAND strings of the first sub-block, comparing a last even result for the NAND string to a last odd result for the NAND string, the last even result is the even result used to determine whether the respective NAND strings erased verified successfully and was obtained prior to determining that erasing of the memory cells for the first sub-block erase verified successfully, the last odd result is the odd result used to determine whether the NAND string erased verified successfully and was obtained prior to determining that erasing of the memory cells for the first sub-block erase verified successfully, and determining that the erasing of the first sub-block failed if a number of NAND strings of the first sub-block that have the last even result different than the last odd result is greater than the second threshold.
 14. The non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to determine that the erasing of the first sub-block failed by: for multiple NAND strings of the first sub-block, comparing a last even result for the NAND string to a last odd result for the NAND string, the last even result is the even result used to determine whether the respective NAND strings erased verified successfully and was obtained prior to determining that erasing of the memory cells for the first sub-block erase verified successfully, the last odd result is the odd result used to determine whether the NAND string erased verified successfully and was obtained prior to determining that erasing of the memory cells for the first sub-block erase verified successfully, and determining that the erasing of the first sub-block failed if a number of NAND strings of the first sub-block that have the last even result different than the last odd result is greater than the second threshold; and the control circuit is configured to determine that the erasing of one or more additional sub-blocks failed in response to determining that the erasing of the first sub-block failed, without testing whether a number of NAND strings of the one or more additional sub-blocks that have the last even result different than the last odd result is greater than the second threshold.
 15. A method of operating non-volatile storage, the non-volatile storage includes a block of non-volatile memory cells arranged in NAND strings, the block is divided into sub-blocks, the method comprising: erasing multiple sub-blocks of the block by applying a plurality of erase voltage pulses to the NAND strings of the multiple sub-blocks; separately, for each sub-block, performing an erase verify process for the NAND strings of the respective sub-block including separately performing erase verify for memory cells connected to even word lines to generate an even result for each NAND string and for memory cells connected to odd word lines to generate an odd result for each NAND string; determining that erasing of the memory cells for a first sub-block of the multiple sub-blocks erase verified successfully because a sum of NAND strings of the first sub-block that failed the erase verify process for memory cells connected to even word lines or failed the erase verify process for memory cells connected to odd word lines is below a first threshold; determining that the erasing of the first sub-block failed, despite determining that erasing of the memory cells for the first sub-block erase verified successfully, because a number of NAND strings of the first sub-block that have the even result different than the odd result is greater than a second threshold; and determining that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed based on and in response to determining that the erasing of the first sub-block failed.
 16. The method of claim 15, wherein: the block includes five sub-blocks including the first sub-block, a second sub-block, a third sub-block, a fourth sub-block and a fifth sub-block; and the determining that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed comprises determining that the erasing of the first sub-block, the second sub-block, the third sub-block, the fourth sub-block and the fifth sub-block all failed based on and in response to determining that the erasing of the first sub-block failed.
 17. The method of claim 15, wherein the block includes four sub-blocks including the first sub-block, a second sub-block, a third sub-block, and a fourth sub-block, the method further comprises: determining that the erasing of the third sub-block failed; and determining that the erasing of the fourth sub-block failed based on and in response to determining that the erasing of the third sub-block failed, the determining that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed comprises determining that the erasing of the second sub-block failed based on and in response to determining that the erasing of the first sub-block failed.
 18. The method of claim 15, wherein: the determining that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed comprises determining that the erasing of all sub-blocks of the block failed based on and in response to determining that the erasing of the first sub-block failed.
 19. A non-volatile storage apparatus, comprising: a block of non-volatile memory cells comprising multiple sub-blocks, each sub-block includes NAND strings connected to a same plurality of word lines; and a control circuit connected to the block of non-volatile memory cells, the control circuit is configured to: apply doses of an erase signal to the block of memory cells, separately for each sub-block, perform erase verify for the NAND strings of the sub-block between and after the doses of the erase signal including separately performing erase verify for memory cells connected to even word lines to generate an even result and performing erase verify for memory cells connected to odd word lines to generate an odd result, separately for each sub-block, determine that erasing of the memory cells for the respective sub-block erase verified successfully when a sum of NAND strings that failed erase verify for memory cells connected to even word lines or failed erase verify for memory cells connected to odd word lines is below a first threshold, for multiple NAND strings of one sub-block of the multiple sub-blocks, compare a last even result for the respective NAND string to a last odd result for the respective NAND string, the last even result is the even result used to determine that the respective NAND strings erased verified successfully and was obtained prior to determining that erasing of the memory cells for the respective sub-block erase verified successfully, the last odd result is the odd result used to determine that the NAND string erased verified successfully and was obtained prior to determining that erasing of the memory cells for the respective sub-block erase verified successfully, determine that the erasing of the one sub-block failed, despite determining that erasing of the memory cells for the respective sub-block erase verified successfully, if a number of NAND strings of the one sub-block that have the last even result different than the last odd result is greater than a second threshold, and determine that the erasing of an additional sub-block of the multiple sub-blocks failed based on and in response to determining that the erasing of the one sub-block failed without determining whether a number of NAND strings of the additional sub-block that have the last even result different than the last odd result is greater than the second threshold.
 20. The non-volatile storage apparatus of claim 19, wherein: the control circuit is configured to determine that the erasing of all sub-blocks failed based on and in response to determining that the erasing of the one sub-block failed despite determining that all sub-blocks of the block erase verified successfully; and the control circuit is configured to retire the block in response to determining that the erasing of all sub-blocks failed. 